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mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD

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This patch updates the flash map layout to guarantee that the
RW_SECTION_B section starts at the 16MB boundary.

Additionally, fix typo in flash descriptor comment, where comment
incorrectly referred to "MTL" instead of "PTL".

TEST=Successfully builds google/fatcat.

Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-10-28 18:54:25 +05:30
commit b1839874be
1 changed files with 9 additions and 9 deletions
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18
src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
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@ -9,6 +9,15 @@ FLASH 32M {
FW_MAIN_A(CBFS)
RW_FWID_A 64
}
# This section starts at the 16M boundary in SPI flash.
# PTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 7680K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
}
RW_MISC 1M {
UNIFIED_MRC_CACHE(PRESERVE) 128K {
RECOVERY_MRC_CACHE 64K
@ -22,15 +31,6 @@ FLASH 32M {
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 24K
}
# This section starts at the 16M boundary in SPI flash.
# MTL does not support a region crossing this boundary,
# because the SPI flash is memory-mapped into two non-
# contiguous windows.
RW_SECTION_B 7680K {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 64
}
RW_LEGACY(CBFS) 1M
RW_UNUSED 2M
# Make WP_RO region align with SPI vendor