vc/intel/fsp/fsp2_0/pantherlake: Update PTL FSP headers to FSP 3442.07

Update Panther lake FSP headers from version 3373.03 to 3442.07

FspmUpd.h: Add below upds
* Vdd2HVoltage
* Vdd1Voltage
* Vdd2LVoltage
* VddqVoltage

FspsUpd.h: Add below upds
* UfsInlineEncryption
* MaxActiveDisplays

MemInfoHob.h:
* FailingChannelMask - Limp Home mode failing channel bitmask

BUG=b:463516609
TEST=Able to build google/fatcat with the latest header changes

Change-Id: Ifd9d3476626f4028ea01eddef23b3b61f5e76d17
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90332
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h

@@ -2463,12 +2463,12 @@ typedef struct {
   UINT8                       DlvrRfiEnable;
 
 /** Offset 0x0949 - Pcore VR Hysteresis time window
-  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  0 is default. Range of PcoreHysteresisWindow from 1ms to 50ms.
 **/
   UINT8                       PcoreHysteresisWindow;
 
 /** Offset 0x094A - Ecore VR Hysteresis time window
-  Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+  0 is default. Range of EcoreHysteresisWindow from 1ms to 50ms.
 **/
   UINT8                       EcoreHysteresisWindow;
 
@@ -2793,7 +2793,8 @@ typedef struct {
   Initialise SOL Init, BIT0 - (0 : Disable VGA Support, 1 : Enable VGA Support),,
   BIT1 - (0 : VGA Text Mode 3, 1 : VGA Graphics Mode 12), BIT2 - (0 : VGA Exit Supported,
   1: NO VGA Exit), BIT3 - (0 : VGA Init During Display Init, 1 - VGA Init During
-  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar)
+  MRC Cold Boot), BIT4 - (0 : Enable Progress Bar, 1 : Disable Progress Bar), BIT5
+  - (0 : VGA Mode 12 16 Color Support, 1 : VGA Mode 12 Monochrome Black and White Support)
   0:VGA Disable, 1:Mode 3 VGA, 2:Mode 12 VGA
 **/
   UINT8                       VgaInitControl;
@@ -3121,7 +3122,31 @@ typedef struct {
 
 /** Offset 0x0B31 - Reserved
 **/
-  UINT8                       Reserved93[55];
+  UINT8                       Reserved93[17];
+
+/** Offset 0x0B42 - VDD2 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2HVoltage;
+
+/** Offset 0x0B44 - VDD1 Voltage
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd1Voltage;
+
+/** Offset 0x0B46 - VDD2L Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      Vdd2LVoltage;
+
+/** Offset 0x0B48 - VDDQ Voltage Override
+  Voltage is multiple of 5mV where 0 means Auto.
+**/
+  UINT16                      VddqVoltage;
+
+/** Offset 0x0B4A - Reserved
+**/
+  UINT8                       Reserved94[30];
 } FSP_M_CONFIG;
 
 /** Fsp M UPD Configuration

src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h

@@ -458,9 +458,17 @@ typedef struct {
 **/
   UINT8                       UfsEnable[2];
 
-/** Offset 0x014D - Reserved
+/** Offset 0x014D - UFS Inline Encryption enable/disable
+  Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
+  to enable Inline Encryption for controller 0 and (0, 1) to enable Inline Encryption
+  for controller 1
+  $EN_DIS
 **/
-  UINT8                       Reserved12[4];
+  UINT8                       UfsInlineEncryption[2];
+
+/** Offset 0x014F - Reserved
+**/
+  UINT8                       Reserved12[2];
 
 /** Offset 0x0151 - Enable/Disable PCIe tunneling for USB4
   Enable/Disable PCIe tunneling for USB4, default is enable
@@ -2026,9 +2034,15 @@ typedef struct {
 **/
   UINT8                       LidStatus;
 
-/** Offset 0x1401 - Reserved
+/** Offset 0x1401 - Select MaxActiveDisplays
+  Max Active Display : 0 - Default VBT, 1 - 1 display, 2 - 2 displays, Maximum supported
+  is 2 displays only
 **/
-  UINT8                       Reserved50[67];
+  UINT8                       MaxActiveDisplays;
+
+/** Offset 0x1402 - Reserved
+**/
+  UINT8                       Reserved50[66];
 
 /** Offset 0x1444 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
   The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.

src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h

@@ -312,7 +312,8 @@ typedef struct _PPR_RESULT_COLUMNS_HOB {
   - DIMM_INFO: Added SerialNumber, TotalWidth and DataWidth
   - DIMM_INFO: Removed SpdModuleMemoryBusWidth
   - MFG ID fields: use HOB_MANUFACTURER_ID_CODE instead of UINT16 for easier parsing
-
+  <b>Revision 4:</b>
+  - Added FailingChannelMask
 **/
 typedef struct {
   UINT8             Revision;
@@ -363,6 +364,7 @@ typedef struct {
   UINT8             MaxRankCapacity;                   ///< Maximum possible rank capacity in [GB]
   UINT16            PprFailingChannelBitMask;          ///< PPR failing channel mask
   BOOLEAN           PprTargetedStatus[PPR_REQUEST_MAX]; ///< PPR status of each Targeted PPR request (0 = Targeted PPR was successful, 1 = PPR failed)
+  UINT8             FailingChannelMask;                 ///< Limp Home mode failing channel bitmask
 } MEMORY_INFO_DATA_HOB;
 
 /**