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soc/inte/*/gpio; Add GPE_EN and GPE_STS register definition

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coreboot needs to set GPE_EN bit for the GPIOs which are wake capable
from s0ix/sleep. Due to GPIO locking mechanism, coreboot/OS will not
be able to write GPE_EN register post GPIO has been locked.

This patch adds support in SoC code to provide correct offset for
GPE_EN and GPE_STS registers to the common code.

Plan is to use this offsets to set GPE_EN bits before GPIO locking
in coreboot which will be part of subsequent CL.

BUG=b:222375516
BRANCH=firmware-brya-14505.B
TEST=Check if code compiles for Brya and correct offset values are printed.

Change-Id: I6b813b30b8b360f8eccbf539b57387310e380560
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Maulik V Vaghela 2022-05-06 10:27:50 +05:30 • committed by Werner Zeh
commit afe840957c
7 changed files with 40 additions and 0 deletions
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2
src/soc/intel/common/block/include/intelblocks/gpio.h
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@ -126,6 +126,8 @@ struct pad_community {
uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */
uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */
uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */
uint16_t gpi_gpe_sts_reg_0; /* offset to GPI GPE STS Reg 0 */
uint16_t gpi_gpe_en_reg_0; /* offset to GPI GPE EN Reg 0 */
uint16_t gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */
uint16_t gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */
uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */