mb/starlabs/byte_adl/cfr: Drop CONFIG guards for CFR elements
The byte_adl is an Alderlake board, so we don't need to do any SoC checks to determine which CFR elements to include. TEST=build/boot starlabs/byte_adl, verify CFR options unchanged. Change-Id: Ie21a873ad7af1504f46db769c3abba00c0e61008 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87067 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1 changed files with 0 additions and 8 deletions
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@ -38,14 +38,12 @@ static const struct sm_object debug_level = SM_DECLARE_ENUM({
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SM_ENUM_VALUE_END },
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});
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#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
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static const struct sm_object gna = SM_DECLARE_BOOL({
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.opt_name = "gna",
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.ui_name = "Gaussian & Neural Accelerator",
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.ui_helptext = "Enable or Disable the Gaussian & Neural Accelerator",
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.default_value = false,
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});
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#endif
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static const struct sm_object me_state = SM_DECLARE_ENUM({
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.opt_name = "me_state",
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@ -84,7 +82,6 @@ static const struct sm_object power_profile = SM_DECLARE_ENUM({
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SM_ENUM_VALUE_END },
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});
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#if CONFIG(SOC_INTEL_ALDERLAKE)
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static const struct sm_object pciexp_aspm = SM_DECLARE_ENUM({
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.opt_name = "pciexp_aspm",
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.ui_name = "PCI ASPM",
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@ -124,7 +121,6 @@ static const struct sm_object pciexp_l1ss = SM_DECLARE_ENUM({
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{ "L1.2", L1_SS_L1_2 },
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SM_ENUM_VALUE_END },
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});
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#endif
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static const struct sm_object reboot_counter = SM_DECLARE_NUMBER({
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.opt_name = "reboot_counter",
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@ -169,9 +165,7 @@ static struct sm_obj_form power = {
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static struct sm_obj_form devices = {
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.ui_name = "Devices",
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.obj_list = (const struct sm_object *[]) {
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#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_ALDERLAKE) || CONFIG(SOC_INTEL_RAPTORLAKE)
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&gna,
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#endif
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NULL
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},
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};
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@ -179,11 +173,9 @@ static struct sm_obj_form devices = {
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static struct sm_obj_form pci = {
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.ui_name = "PCI",
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.obj_list = (const struct sm_object *[]) {
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#if CONFIG(SOC_INTEL_ALDERLAKE)
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&pciexp_clk_pm,
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&pciexp_aspm,
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&pciexp_l1ss,
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#endif
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NULL
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},
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};
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