Coding-style, whitespace, and Doxygen-fixes for util.c (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@950 f3766cd6-281f-0410-b1cd-43a5c92072e9
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Uwe Hermann
parent
84b3e13596
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1 changed files with 115 additions and 98 deletions
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@ -1,10 +1,8 @@
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/*
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* K8 northbridge utilities (dump routing registers). Designed to be called at any time.
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com>
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* Original Python code
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* Convert to c (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,6 +18,11 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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/*
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* K8 northbridge utilities (dump routing registers).
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* Designed to be called at any time.
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*/
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#include <mainboard.h>
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#include <console.h>
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#include <string.h>
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@ -37,45 +40,46 @@
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#define BITS(r, shift, mask) (((r>>shift)&mask))
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/**
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* return "R" if the register has read-enable bit set
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/**
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* Return "R" if the register has read-enable bit set.
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*/
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static char *re(u32 i)
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{
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if (i & 1)
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return "R";
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else
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return "";
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return ((i & 1) ? "R" : "");
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}
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/**
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* return "W" if the register has read-enable bit set
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/**
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* Return "W" if the register has read-enable bit set.
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* TODO: Shouldn't this be "write-enable"?
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*/
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static char *we(u32 i)
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{
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if (i & 1)
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return "W";
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else
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return "";
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return ((i & 1) ? "W" : "");
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}
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/**
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* return a string containing the interleave settings.
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/**
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* Return a string containing the interleave settings.
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*/
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static char *ileave(u32 base)
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{
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switch((base >> 8) & 7) {
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case 0: return "No interleave";
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case 1: return "2 nodes";
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case 3: return "4 nodes";
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case 7: return "8 nodes";
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default: return "Reserved";
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/* TODO: Are these fallthroughs intentional? */
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switch ((base >> 8) & 7) {
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case 0:
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return "No interleave";
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case 1:
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return "2 nodes";
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case 3:
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return "4 nodes";
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case 7:
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return "8 nodes";
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default:
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return "Reserved";
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}
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}
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/**
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* Return the node number.
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* For one case (config registers) these are not the right bit fields.
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* Return the node number.
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* For one case (config registers) these are not the right bit fields.
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*/
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static int node(u32 reg)
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{
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@ -83,152 +87,165 @@ static int node(u32 reg)
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}
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/**
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* Return the link number.
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* For one case (config registers) these are not the right bit fields.
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* Return the link number.
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* For one case (config registers) these are not the right bit fields.
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*/
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static int link(u32 reg)
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{
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return BITS(reg, 4, 0x3);
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}
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/**
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* Print the dram routing info for one base/limit pair.
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* Show base, limit, dest node, dest link on that node, read and write enable, and
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* interleave information.
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* @param level printing level
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* Print the DRAM routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and interleave information.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param limit Limit register
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* @param lim Limit register
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*/
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void showdram(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
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which, (((u64)base&0xffff0000)<<8),
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(((u64)lim&0xffff0000)<<8)+0xffffff,
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node(lim), re(base), we(base),
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ileave(base), (lim>>8)&3);
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printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
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which, (((u64) base & 0xffff0000) << 8),
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(((u64) lim & 0xffff0000) << 8) + 0xffffff,
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node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
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}
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/**
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* Print the config routing info for a config register.
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* Show base, limit, dest node, dest link on that node, read and write enable, and
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* device number compare enable
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* @param level printing level
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* Print the config routing info for a config register.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and device number compare enable
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*
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* @param level Printing level
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* @param which Register number
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* @param reg config register
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* @param reg Config register
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*/
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void showconfig(int level, u8 which, u32 reg)
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{
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/* don't use node() and link() here */
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printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s CE %d\n",
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which, BITS(reg, 24, 0xff), BITS(reg, 16, 0xff),
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BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
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re(reg), we(reg), BITS(reg, 2, 0x1));
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/* Don't use node() and link() here. */
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printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s CE %d\n",
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which, BITS(reg, 24, 0xff), BITS(reg, 16, 0xff),
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BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
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re(reg), we(reg), BITS(reg, 2, 0x1));
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}
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/**
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* Print the pciio routing info for one base/limit pair.
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* Show base, limit, dest node, dest link on that node, read and write enable, and
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* VGA and ISA Enable.
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* @param level printing level
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* Print the PCIIO routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and VGA and ISA Enable.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param limit Limit register
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* @param lim Limit register
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*/
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void showpciio(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
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which, BITS(base, 12, 0x3fff)<<12,
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(BITS(lim, 12, 0x3fff)<<12) + 0xfff,
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node(lim), link(lim),
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re(base), we(base),
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BITS(base, 4, 0x1), BITS(base, 5, 0x1));
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printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
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which, BITS(base, 12, 0x3fff) << 12,
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(BITS(lim, 12, 0x3fff) << 12) + 0xfff, node(lim), link(lim),
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re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1));
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}
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/**
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* Print the mmio routing info for one base/limit pair.
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* Show base, limit, dest node, dest link on that node, read and write enable, and
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* CPU Disable, Lock, and Non-posted.
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* @param level printing level
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* Print the MMIO routing info for one base/limit pair.
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*
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* Show base, limit, dest node, dest link on that node, read and write
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* enable, and CPU Disable, Lock, and Non-posted.
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*
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* @param level Printing level
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* @param which Register number
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* @param base Base register
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* @param limit Limit register
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* @param lim Limit register
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*/
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void showmmio(int level, u8 which, u32 base, u32 lim)
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{
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printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, CPU disable %d, Lock %d, Non posted %d\n",
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which, ((u64)BITS(base, 0, 0xffffff00))<<8,
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(((u64)BITS(lim, 0, 0xffffff00))<<8)+0xffff,
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node(lim), link(lim), re(base), we(base),
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BITS(base, 4, 0x1),
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BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
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printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, "
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"CPU disable %d, Lock %d, Non posted %d\n",
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which, ((u64) BITS(base, 0, 0xffffff00)) << 8,
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(((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, node(lim),
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link(lim), re(base), we(base), BITS(base, 4, 0x1),
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BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
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}
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/**
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* Show all dram routing registers. This function is callable at any time.
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* @param level The debug level
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* @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
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* Show all DRAM routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showalldram(int level, u32 dev)
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{
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u8 reg;
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for(reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
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for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
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u32 base = pci_conf1_read_config32(dev, reg);
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u32 lim = pci_conf1_read_config32(dev,reg+4);
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u32 lim = pci_conf1_read_config32(dev, reg + 4);
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showdram(level, reg, base, lim);
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}
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}
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}
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/**
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* Show all mmio routing registers. This function is callable at any time.
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* @param level The debug level
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* @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
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* Show all MMIO routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showallmmio(int level, u32 dev)
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{
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u8 reg;
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for(reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
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for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
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u32 base = pci_conf1_read_config32(dev, reg);
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u32 lim = pci_conf1_read_config32(dev,reg+4);
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u32 lim = pci_conf1_read_config32(dev, reg + 4);
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showmmio(level, reg, base, lim);
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}
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}
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}
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/**
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* Show all pciio routing registers. This function is callable at any time.
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* @param level The debug level
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* @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
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* Show all PCIIO routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showallpciio(int level, u32 dev)
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{
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u8 reg;
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for(reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
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for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
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u32 base = pci_conf1_read_config32(dev, reg);
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u32 lim = pci_conf1_read_config32(dev,reg+4);
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u32 lim = pci_conf1_read_config32(dev, reg + 4);
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showpciio(level, reg, base, lim);
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}
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}
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}
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/**
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* Show all config routing registers. This function is callable at any time.
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* @param level The debug level
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* @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
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* Show all config routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showallconfig(int level, u32 dev)
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{
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u8 reg;
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for(reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
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for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
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u32 val = pci_conf1_read_config32(dev, reg);
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showconfig(level, reg, val);
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}
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}
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}
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/**
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* Show all routing registers. This function is callable at any time.
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* @param level The debug level
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* @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
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* Show all routing registers. This function is callable at any time.
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*
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* @param level The debug level.
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* @param dev A 32-bit number in the standard bus/dev/fn format which is used
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* raw config space.
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*/
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void showallroutes(int level, u32 dev)
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{
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