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ACPI: Separate ChromeOS NVS in ASL

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For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.

More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.

Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-01-12 15:23:25 +02:00
commit ae7ac8a723
14 changed files with 41 additions and 59 deletions
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4
src/soc/intel/apollolake/acpi/globalnvs.asl
View file

@ -28,8 +28,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
ELNG, 64, // 0x35 - 0x3C EPC Length
A4GB, 64, // 0x3D - 0x44 Base of above 4GB MMIO Resource
A4GS, 64, // 0x45 - 0x4C Length of above 4GB MMIO Resource
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}

4
src/soc/intel/baytrail/acpi/globalnvs.asl
View file

@ -42,10 +42,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CMEM, 32, /* 0x30 - CBMEM TOC */
TOLM, 32, /* 0x34 - Top of Low Memory */
CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
/* Set flag to enable USB charging in S3 */

4
src/soc/intel/braswell/acpi/globalnvs.asl
View file

@ -44,10 +44,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CMEM, 32, /* 0x30 - CBMEM TOC */
TOLM, 32, /* 0x34 - Top of Low Memory */
CBMC, 32, /* 0x38 - coreboot mem console pointer */
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
/* Set flag to enable USB charging in S3 */

4
src/soc/intel/broadwell/pch/acpi/globalnvs.asl
View file

@ -34,10 +34,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
/* Set flag to enable USB charging in S3 */

4
src/soc/intel/common/block/acpi/acpi/globalnvs.asl
View file

@ -26,8 +26,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
UIOR, 8, // 0x2f - UART debug controller init on S3 resume
A4GB, 64, // 0x30 - 0x37 Base of above 4GB MMIO Resource
A4GS, 64, // 0x38 - 0x3f Length of above 4GB MMIO Resource
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}

4
src/soc/intel/skylake/acpi/globalnvs.asl
View file

@ -46,10 +46,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
ELNG, 64, // 0x4C - 0x53 EPC Length
A4GB, 64, // 0x54 - 0x5B Base of above 4GB MMIO Resource
A4GS, 64, // 0x5C - 0x63 Length of above 4GB MMIO Resource
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
}
/* Set flag to enable USB charging in S3 */