From ae435c014c48517c0a89e04cac629ad681703e44 Mon Sep 17 00:00:00 2001 From: Mengqi Zhang Date: Sun, 22 Dec 2024 16:32:30 +0800 Subject: [PATCH] soc/mediatek/mt8189: Configure and early initialize eMMC Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. BUG=b:379008996 BRANCH=none TEST=build pass and run "storage init" in depthcharge shell on MTK EVB firmware-shell: storage init * 0: mtk_mmc 1 devices total Signed-off-by: Mengqi Zhang Change-Id: I82f2a155b810a8b9608d70fe0c015e6054d0be00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87862 Reviewed-by: Yu-Ping Wu Tested-by: build bot (Jenkins) Reviewed-by: Yidi Lin --- src/soc/mediatek/mt8189/Makefile.mk | 1 + .../mediatek/mt8189/include/soc/addressmap.h | 2 + src/soc/mediatek/mt8189/msdc.c | 40 +++++++++++++++++++ 3 files changed, 43 insertions(+) create mode 100644 src/soc/mediatek/mt8189/msdc.c diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 32c76cc6d5..2890564792 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -38,6 +38,7 @@ ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c mcupm.c ramstage-y += ../common/memory.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c ramstage-y += ../common/mt6315.c mt6315.c ramstage-y += ../common/mt6359p.c mt6359p.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h index 61999e03b0..5a127f65aa 100644 --- a/src/soc/mediatek/mt8189/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -58,6 +58,7 @@ enum { PERICFG_AO_BASE = IO_PHYS + 0x01036000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000, AUDIO_BASE = IO_PHYS + 0x01050000, + MSDC0_BASE = IO_PHYS + 0x01230000, SSUSB_IPPC_BASE = IO_PHYS + 0x01263E00, UFSHCI_BASE = IO_PHYS + 0x012B0000, UFS0_AO_CFG_BASE = IO_PHYS + 0x012B8000, @@ -94,6 +95,7 @@ enum { IMP_IIC_WRAP_S_BASE = IO_PHYS + 0x01D74000, IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, + MSDC0_TOP_BASE = IO_PHYS + 0x01E70000, EFUSEC_BASE = IO_PHYS + 0x01F10000, IOCFG_RT_BASE = IO_PHYS + 0x01F20000, IMP_IIC_WRAP_EN_BASE = IO_PHYS + 0x01F32000, diff --git a/src/soc/mediatek/mt8189/msdc.c b/src/soc/mediatek/mt8189/msdc.c new file mode 100644 index 0000000000..1ebb78ef41 --- /dev/null +++ b/src/soc/mediatek/mt8189/msdc.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.8 + */ + +#include +#include +#include +#include +#include + +static const struct pad_func emmc_pins[] = { + PAD_FUNC_DOWN(EMMC_CLK, MSDC0_CLK), + PAD_FUNC_DOWN(EMMC_DSL, MSDC0_DSL), + PAD_FUNC_UP(EMMC_CMD, MSDC0_CMD), + PAD_FUNC_UP(EMMC_DAT0, MSDC0_DAT0), + PAD_FUNC_UP(EMMC_DAT1, MSDC0_DAT1), + PAD_FUNC_UP(EMMC_DAT2, MSDC0_DAT2), + PAD_FUNC_UP(EMMC_DAT3, MSDC0_DAT3), + PAD_FUNC_UP(EMMC_DAT4, MSDC0_DAT4), + PAD_FUNC_UP(EMMC_DAT5, MSDC0_DAT5), + PAD_FUNC_UP(EMMC_DAT6, MSDC0_DAT6), + PAD_FUNC_UP(EMMC_DAT7, MSDC0_DAT7), +}; + +void mtk_msdc_configure_emmc(bool is_early_init) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(emmc_pins); i++) { + gpio_set_mode(emmc_pins[i].gpio, emmc_pins[i].func); + gpio_set_pull(emmc_pins[i].gpio, GPIO_PULL_ENABLE, emmc_pins[i].select); + gpio_set_driving(emmc_pins[i].gpio, GPIO_DRV_6_MA); + } + + if (is_early_init) + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); +}