From ad78fc535a551fee3fb476fa44efff42272d2683 Mon Sep 17 00:00:00 2001 From: Luca Lai Date: Tue, 10 Jun 2025 21:31:02 +0800 Subject: [PATCH] mb/trulo/var/pujjolo: Add single ram configuration Pujjolo project is going to have single RAM devices,so add single ram configuration. BUG=b:395763555 BRANCH=none TEST=Build and boot to OS. Verify functions work. Change-Id: I92b0bd1e05276c170d35ce20508cc6f439104442 Signed-off-by: Luca Lai Reviewed-on: https://review.coreboot.org/c/coreboot/+/88027 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal Reviewed-by: Eric Lai --- src/mainboard/google/brya/Kconfig | 1 + src/mainboard/google/brya/variants/pujjolo/gpio.c | 12 +++++++----- .../google/brya/variants/pujjolo/memory.c | 14 ++++++++++++++ 3 files changed, 22 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 938bbe220e..8051ba989a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -499,6 +499,7 @@ config BOARD_GOOGLE_PUJJOLO select DRIVERS_I2C_SX9324 select DRIVERS_GFX_GENERIC select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select ENFORCE_MEM_CHANNEL_DISABLE select HAVE_WWAN_POWER_SEQUENCE select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION diff --git a/src/mainboard/google/brya/variants/pujjolo/gpio.c b/src/mainboard/google/brya/variants/pujjolo/gpio.c index 7717efe1ac..96a0ef48f5 100644 --- a/src/mainboard/google/brya/variants/pujjolo/gpio.c +++ b/src/mainboard/google/brya/variants/pujjolo/gpio.c @@ -172,8 +172,8 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG), /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), - /* E9 : NC */ - PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), + /* E9 : NC ==> DIMM_CHANNEL_SELECT */ + PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG), /* E10 : EN_PP3300_WLAN_X */ PAD_CFG_GPO(GPP_E10, 0, DEEP), /* E11 : TCHSCR_INT_ODL */ @@ -440,9 +440,11 @@ static const struct pad_config early_gpio_table[] = { * later on in ramstage. Since reset signal is asserted in bootblock, it results in * FPMCU not working after a S3 resume. This is a known issue. */ - PAD_CFG_GPO(GPP_E7, 0, DEEP), - /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO(GPP_E7, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* E9 : DIMM_CHANNEL_SELECT */ + PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG), /* E17 : WWAN_RST_L */ PAD_CFG_GPO(GPP_E17, 0, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ diff --git a/src/mainboard/google/brya/variants/pujjolo/memory.c b/src/mainboard/google/brya/variants/pujjolo/memory.c index bb80ee15ec..876e96782c 100644 --- a/src/mainboard/google/brya/variants/pujjolo/memory.c +++ b/src/mainboard/google/brya/variants/pujjolo/memory.c @@ -109,3 +109,17 @@ void variant_get_spd_info(struct mem_spd *spd_info) spd_info->topo = MEM_TOPO_MEMORY_DOWN; spd_info->cbfs_index = variant_memory_sku(); } + +uint8_t mb_get_channel_disable_mask(void) +{ + /* + * GPP_E9 High -> One RAM Chip + * GPP_E9 Low -> Two RAM Chip + */ + if (gpio_get(GPP_E9)) { + /* Disable all other channels except first two on each controller */ + printk(BIOS_INFO, "Device only supports one DIMM.\n"); + return (BIT(2) | BIT(3)); + } + return 0; +}