diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 5083e577ad..74812f31bf 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -125,7 +125,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT;
 
 	/* Configure VT-d */
-	tconfig->VtdDisable = 0;
+	tconfig->VtdDisable = !get_uint_option("vtd", 1);
 
 	/* Set HECI1 PCI BAR address */
 	m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;