From ad3bc94dbd4ec7c37738a9b88a071fc975b93fec Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 15 Jan 2025 13:12:08 +0000 Subject: [PATCH] soc/intel/pantherlake: Enable FSP debug log level control using CBFS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/86002 Reviewed-by: Jérémy Compostella Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- src/soc/intel/pantherlake/fsp_params.c | 3 ++- src/soc/intel/pantherlake/romstage/fsp_params.c | 10 +++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index dfc47c6988..a78059d512 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -685,7 +686,7 @@ static void arch_silicon_init_params(FSPS_ARCH2_UPD *s_arch_cfg) /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) - && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + && CONFIG(FSP_ENABLE_SERIAL_DEBUG) && fsp_get_pcd_debug_log_level()) s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *) fsp_debug_event_handler); diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 2bb4d21c6a..7d965fd496 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -320,9 +321,12 @@ static void fsp_control_log_level(FSPM_UPD *mupd, bool is_enabled) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() : - FSP_LOG_LEVEL_DISABLE; - fsp_set_debug_level(m_cfg, log_level, log_level); + enum fsp_log_level fsp_log_level = is_enabled ? fsp_get_pcd_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + enum fsp_log_level mrc_log_level = is_enabled ? fsp_get_mrc_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + + fsp_set_debug_level(m_cfg, fsp_log_level, mrc_log_level); if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) || (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) {