From ace2e540d00327fb9598dcf65551d18a1f07cffb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 10 Nov 2025 13:15:26 +0530 Subject: [PATCH] soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value The console UART base address for Panther Lake is being updated from 0xfe036000 to 0xfe02c000 (as per FSP version 3272). This correction ensures the console initializes with the correct UART base address. TEST=Able to get FSP debug log while building google/fatcat. Change-Id: Ic123189fb5689318a4940edcfcf206c32e3ccf26 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/89981 Tested-by: build bot (Jenkins) Reviewed-by: Derek Huang --- src/soc/intel/pantherlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index a0a39bc765..365d8e2736 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -320,7 +320,7 @@ config SOC_INTEL_USB3_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe036000 + default 0xfe02c000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate