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mainboard: Add 2S Intel Birch Stream MiTAC Computing R520G6SB

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The R520G6SB server represents the next generation of the M50FCP2UR
Intel Server System, delivering cutting-edge performance and
versatility tailored for demanding data center and enterprise
workloads. Designed as a 2U dual-socket (2S) Birch Stream SP server
system, it integrates advanced features to meet demanding computing,
networking, and AI-driven application requirements.

Tested:
 - USB: Front Panel 2 USB ports and 1 USB port on DCSCM
 - PCIe: J1_MXIO_SLOT1 ~ J1_MXIO_SLOT5 (with PCIe SATA controller)
 - M.2: M2_CN1, M2_CN2
 - Mini Display Port
 - Flash firmware from BMC's redfish interface (Out-of-band)

Build with Linux payload and Intel proprietary FSP.
Installed with dual Intel® Xeon® 6756E, one Micron 64GB DDR5
RDIMM 4800 and boots to Ubuntu 22.04.5 LTS (6.8.0-57-generic).

Change-Id: I0590c82c9763bd07348bd86b134007ea4ed71d7a
Signed-off-by: Schumi Chu <schumi.chu@mitaccomputing.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87574
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Schumi Chu 2025-05-08 13:59:20 +08:00 • committed by Matt DeVillier
commit ace18dea15
13 changed files with 543 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

54
configs/builder/config.mitaccomputing.r520g6sb Normal file
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# Type this in coreboot root directory to get a working .config:
# make defconfig KBUILD_DEFCONFIG=configs/builder/config.mitaccomputing.sc513g6
#
# [RO] Board Configurations
#
CONFIG_VENDOR_MITAC_COMPUTING=y
CONFIG_BOARD_MITAC_COMPUTING_R520G6SB=y
CONFIG_HAVE_CONFIGURABLE_RAMSTAGE=y
CONFIG_CONFIGURABLE_RAMSTAGE=y
CONFIG_NO_GFX_INIT=y
CONFIG_HAVE_IFD_BIN=y
CONFIG_HAVE_PBP_BIN=n
CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_PAYLOAD_LINUX=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_CONSOLE_SERIAL_115200=y
CONFIG_COREBOOT_ROMSIZE_KB_65536=y
#
# [RW] IFWI Ingredients
#
CONFIG_IFD_BIN_PATH="site-local/r520g6sb/descriptor.bin"
CONFIG_PBP_BIN_PATH=""
CONFIG_CPU_UCODE_BINARIES="site-local/r520g6sb/ucode.mcb"
CONFIG_FSP_T_FILE="site-local/r520g6sb/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/r520g6sb/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/r520g6sb/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/"
CONFIG_PAYLOAD_FILE="site-local/r520g6sb/bzImage"
CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
#
# [RW] Debug Settings
#
CONFIG_CONSOLE_POST=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_VERIFY_HOBS=y
CONFIG_DISPLAY_MTRRS=y
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
CONFIG_HAVE_DEBUG_GPIO=y
CONFIG_DEBUG_GPIO=y

38
src/mainboard/mitaccomputing/r520g6sb/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_MITAC_COMPUTING_R520G6SB
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_65536
select SOC_INTEL_GRANITERAPIDS
select SUPERIO_ASPEED_AST2400
select CONSOLE_OVERRIDE_LOGLEVEL
select HAVE_ACPI_TABLES
select IPMI_KCS
select IPMI_KCS_ROMSTAGE
select VPD
select OCP_VPD
select MEMORY_MAPPED_TPM
config CARDBUS_PLUGIN_SUPPORT
bool
default n
config MAINBOARD_DIR
string
default "mitaccomputing/r520g6sb"
config MAINBOARD_PART_NUMBER
string
default "R520G6SB"
config FMDFILE
string
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
config DIMM_MAX
int
default 32
endif

4
src/mainboard/mitaccomputing/r520g6sb/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_MITAC_COMPUTING_R520G6SB
bool "R520G6SB"

8
src/mainboard/mitaccomputing/r520g6sb/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
romstage-y += romstage.c
romstage-y += config/dimm_slot.c
romstage-y += config/iio.c
ramstage-y += config/dimm_slot.c
ramstage-y += ramstage.c

12
src/mainboard/mitaccomputing/r520g6sb/board.fmd Normal file
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FLASH 64M {
SI_ALL 48M {
SI_DESC@0x0 0x1000
}
SI_BIOS 16M {
RW_MRC_CACHE 0x10000
FMAP 0x800
RW_VPD(PRESERVE) 0x4000
RO_VPD(PRESERVE) 0x4000
COREBOOT(CBFS)
}
}

6
src/mainboard/mitaccomputing/r520g6sb/board_info.txt Normal file
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Vendor name: MiTAC Computing
Board name: R520G6SB
Category: eval
ROM protocol: SPI
ROM socketed: y
Flashrom support: y

25
src/mainboard/mitaccomputing/r520g6sb/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <console/console.h>
#include <intelblocks/lpc_lib.h>
#include <soc/intel/common/block/lpc/lpc_def.h>
#include <superio/aspeed/ast2400/ast2400.h>
#include <superio/aspeed/common/aspeed.h>
#define ASPEED_SIO_PORT 0x2E
void bootblock_mainboard_early_init(void)
{
/* Enable eSPI decoding for com1 (0x3f8), com2 (0x2f8) and superio (0x2e) */
lpc_io_setup_comm_a_b();
lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F);
if (CONFIG_UART_FOR_CONSOLE == 0 || CONFIG_UART_FOR_CONSOLE == 1) {
/* Set up Super I/O com1 or com2 */
const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
} else {
die("COMs other than COM1/COM2 not supported\n");
}
}

46
src/mainboard/mitaccomputing/r520g6sb/config/dimm_slot.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <commonlib/helpers.h>
#include <soc/dimm_slot.h>
static const struct dimm_slot_config dimm_slot_config_table[] = {
/* socket, channel, dimm, dev_locator, bank_locator, asset_tag */
{0, 0, 0, "CPU0_DIMM_A1", "BANK 0", "CPU0_DIMM_A1_AssetTag"},
{0, 0, 1, "CPU0_DIMM_A2", "BANK 1", "CPU0_DIMM_A2_AssetTag"},
{0, 1, 0, "CPU0_DIMM_B1", "BANK 2", "CPU0_DIMM_B1_AssetTag"},
{0, 1, 1, "CPU0_DIMM_B2", "BANK 3", "CPU0_DIMM_B2_AssetTag"},
{0, 2, 0, "CPU0_DIMM_C1", "BANK 4", "CPU0_DIMM_C1_AssetTag"},
{0, 2, 1, "CPU0_DIMM_C2", "BANK 5", "CPU0_DIMM_C2_AssetTag"},
{0, 3, 0, "CPU0_DIMM_D1", "BANK 6", "CPU0_DIMM_D1_AssetTag"},
{0, 3, 1, "CPU0_DIMM_D2", "BANK 7", "CPU0_DIMM_D2_AssetTag"},
{0, 4, 0, "CPU0_DIMM_E1", "BANK 8", "CPU0_DIMM_E1_AssetTag"},
{0, 4, 1, "CPU0_DIMM_E2", "BANK 9", "CPU0_DIMM_E2_AssetTag"},
{0, 5, 0, "CPU0_DIMM_F1", "BANK 10", "CPU0_DIMM_F1_AssetTag"},
{0, 5, 1, "CPU0_DIMM_F2", "BANK 11", "CPU0_DIMM_F2_AssetTag"},
{0, 6, 0, "CPU0_DIMM_G1", "BANK 12", "CPU0_DIMM_G1_AssetTag"},
{0, 6, 1, "CPU0_DIMM_G2", "BANK 13", "CPU0_DIMM_G2_AssetTag"},
{0, 7, 0, "CPU0_DIMM_H1", "BANK 14", "CPU0_DIMM_H1_AssetTag"},
{0, 7, 1, "CPU0_DIMM_H2", "BANK 15", "CPU0_DIMM_H2_AssetTag"},
{1, 0, 0, "CPU1_DIMM_A1", "BANK 16", "CPU1_DIMM_A1_AssetTag"},
{1, 0, 1, "CPU1_DIMM_A2", "BANK 17", "CPU1_DIMM_A2_AssetTag"},
{1, 1, 0, "CPU1_DIMM_B1", "BANK 18", "CPU1_DIMM_B1_AssetTag"},
{1, 1, 1, "CPU1_DIMM_B2", "BANK 19", "CPU1_DIMM_B2_AssetTag"},
{1, 2, 0, "CPU1_DIMM_C1", "BANK 20", "CPU1_DIMM_C1_AssetTag"},
{1, 2, 1, "CPU1_DIMM_C2", "BANK 21", "CPU1_DIMM_C2_AssetTag"},
{1, 3, 0, "CPU1_DIMM_D1", "BANK 22", "CPU1_DIMM_D1_AssetTag"},
{1, 3, 1, "CPU1_DIMM_D2", "BANK 23", "CPU1_DIMM_D2_AssetTag"},
{1, 4, 0, "CPU1_DIMM_E1", "BANK 24", "CPU1_DIMM_E1_AssetTag"},
{1, 4, 1, "CPU1_DIMM_E2", "BANK 25", "CPU1_DIMM_E2_AssetTag"},
{1, 5, 0, "CPU1_DIMM_F1", "BANK 26", "CPU1_DIMM_F1_AssetTag"},
{1, 5, 1, "CPU1_DIMM_F2", "BANK 27", "CPU1_DIMM_F2_AssetTag"},
{1, 6, 0, "CPU1_DIMM_G1", "BANK 28", "CPU1_DIMM_G1_AssetTag"},
{1, 6, 1, "CPU1_DIMM_G2", "BANK 29", "CPU1_DIMM_G2_AssetTag"},
{1, 7, 0, "CPU1_DIMM_H1", "BANK 30", "CPU1_DIMM_H1_AssetTag"},
{1, 7, 1, "CPU1_DIMM_H2", "BANK 31", "CPU1_DIMM_H2_AssetTag"},
};
const struct dimm_slot_config *get_dimm_slot_config_table(int *size)
{
*size = ARRAY_SIZE(dimm_slot_config_table);
return dimm_slot_config_table;
}

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src/mainboard/mitaccomputing/r520g6sb/config/iio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <soc/iio.h>
static const struct iio_pe_config iio_config_table[] = {
{_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
/*
* CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated
* then port settings are listed accordingly. The minimal port elements are x2.
* If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
* disabled.
*/
{_IIO_PE_CFG_STRUCT(0x0, PE1, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3),
_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
_IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x6),
}},
{_IIO_PE_CFG_STRUCT(0x0, PE2, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x7),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x0, PE3, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x8),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x0, PE4, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x9),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xA),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x0, PE5, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xB),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0xC),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
_IIO_PE_CFG_DISABLED(0x0, PEa),
_IIO_PE_CFG_DISABLED(0x0, PEb),
_IIO_PE_CFG_DISABLED(0x0, PEc),
_IIO_PE_CFG_DISABLED(0x0, PEd),
{_IIO_PE_CFG_STRUCT(0x1, PE0, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x1),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x1, PE1, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x2),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x3),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x1, PE2, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x4),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x1, PE3, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x5),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x1, PE4, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x6),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x7),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
{_IIO_PE_CFG_STRUCT(0x1, PE5, CB_IIO_BIFURCATE_x8xxx8xx, PE_TYPE_PCIE) {
/* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x8),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x9),
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
_IIO_PORT_CFG_STRUCT_DISABLED,
}},
_IIO_PE_CFG_DISABLED(0x1, PEa),
_IIO_PE_CFG_DISABLED(0x1, PEb),
_IIO_PE_CFG_DISABLED(0x1, PEc),
_IIO_PE_CFG_DISABLED(0x1, PEd),
};
const struct iio_pe_config *get_iio_config_table(int *size)
{
*size = ARRAY_SIZE(iio_config_table);
return iio_config_table;
}

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src/mainboard/mitaccomputing/r520g6sb/devicetree.cb Normal file
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## SPDX-License-Identifier: GPL-2.0-or-later
chip soc/intel/xeon_sp/gnr
# configure LPC generic IO decode ranges
# [bits 31..24: reserved]
# [bits 23..18: io decode address mask <7..2>]
# [bits 17..16: reserved]
# [bits 15..2 : io decode dword aligned address <15..2>]
# [bit 1 : reserved]
# [bit 0 : enabled]
register "gen1_dec" = "0x00000CA1" # IPMI KCS
# configure FSP debug settings
register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE
device domain 0 on
device pci 1f.0 on
chip superio/common
device pnp 2e.0 on
chip superio/aspeed/ast2400
register "use_espi" = "1"
device pnp 2e.2 on # SUART1
io 0x60 = 0x3f8 # PNP_IDX_IO0
irq 0x70 = 4 # PNP_IDX_IRQ0
end
device pnp 2e.3 on # SUART2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end
end
end
chip drivers/ipmi
device pnp ca2.0 on end # BMC KCS
register "wait_for_bmc" = "1"
register "bmc_boot_timeout" = "60"
end
end
end
end

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src/mainboard/mitaccomputing/r520g6sb/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <soc/intel/xeon_sp/gnr/acpi/uncore.asl>
#include <soc/intel/xeon_sp/gnr/acpi/gpe.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
#include <commonlib/include/commonlib/console/post_codes.h>
#include <arch/x86/acpi/post.asl>
#include <arch/x86/acpi/debug.asl>
}

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src/mainboard/mitaccomputing/r520g6sb/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <smbios.h>
#include <soc/dimm_slot.h>
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSPS_UPD *params)
{
}
/*
* TODO: SMBIOS info in src/lib/smbios_defaults.c could be overridden based on needs
*/
smbios_wakeup_type smbios_system_wakeup_type(void)
{
return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
}
u8 smbios_mainboard_feature_flags(void)
{
return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE;
}
smbios_enclosure_type smbios_mainboard_enclosure_type(void)
{
return SMBIOS_ENCLOSURE_RACK_MOUNT_CHASSIS;
}
void smbios_fill_dimm_locator(const struct dimm_info *dimm, struct smbios_type17 *t)
{
int size;
const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
for (int i = 0; i < size; i++) {
if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
const char *locator = dimm_slot_config_table[i].dev_locator;
t->device_locator = smbios_add_string(t->eos, locator);
locator = dimm_slot_config_table[i].bank_locator;
t->bank_locator = smbios_add_string(t->eos, locator);
}
}
}
void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbios_type17 *t)
{
int size;
const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
for (int i = 0; i < size; i++) {
if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i],
dimm->soc_num, dimm->channel_num, dimm->dimm_num)) {
const char *asset_tag = dimm_slot_config_table[i].asset_tag;
t->asset_tag = smbios_add_string(t->eos, asset_tag);
}
}
}

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src/mainboard/mitaccomputing/r520g6sb/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <drivers/ipmi/ipmi_if.h>
#include <drivers/ocp/include/vpd.h>
#include <drivers/vpd/vpd.h>
#include <fmap_config.h>
#include <device/device.h>
#include <soc/ddr.h>
#include <soc/dimm_slot.h>
#include <soc/iio.h>
#include <soc/romstage.h>
#include <static.h>
#include "chip.h"
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
/* FSP log outputs */
const config_t *config = config_of_soc();
m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base;
m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT);
m_cfg->DebugPrintLevel = config->debug_print_level;
m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL,
FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4);
/* Early connect BMC, e.g. to query configuration parameters */
if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS)
printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n",
CONFIG_BMC_KCS_BASE);
/* Set BIOS region UPD, otherwise MTRR might set incorrectly during TempRamExit API */
m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START;
m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE;
printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase);
printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize);
/* IIO init */
int size;
const struct iio_pe_config *iio_config_table = get_iio_config_table(&size);
soc_config_iio_pe_ports(mupd, iio_config_table, size);
}
bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm)
{
int size;
const struct dimm_slot_config *dimm_slot_config_table = get_dimm_slot_config_table(&size);
for (int i = 0; i < size; i++) {
if (DIMM_SLOT_EQUAL(dimm_slot_config_table[i], socket, channel, dimm))
return true;
}
return false;
}