erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

nyan: nyan_big: Mark the address range covering the SRAM as cachable.

Browse source 
The SRAM is very likely faster than going all the way out to DRAM for data,
but I don't think it's part of the cores themselves and won't be as fast as
the L1 caches. Enabling caching for this region reduces the time it takes to
get to the payload by about 75% when serial output is disabled and the main
part of display init is commented out.

BUG=chrome-os-partner:25467
TEST=Built and booted on nyan.
BRANCH=None

Change-Id: I7ff26dea9d50e7d9a76e598e5654488481286b35
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/188459
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2014-03-01 03:27:00 -08:00 • committed by chrome-internal-fetch
commit ac8b9b3049
2 changed files with 12 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/mainboard/google/nyan/romstage.c
View file

@ -89,10 +89,16 @@ static void __attribute__((noinline)) romstage(void)
u32 dram_size = dram_end - dram_start;
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);

6
src/mainboard/google/nyan_big/romstage.c
View file

@ -89,10 +89,16 @@ static void __attribute__((noinline)) romstage(void)
u32 dram_size = dram_end - dram_start;
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);