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soc/mediatek: Refactor MMU operation for L2C SRAM and DMA

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Refactor mmu operation by
- moving mtk_soc_disable_l2c_sram to l2c_ops.c
- keeping mtk_soc_after_dram in mmu_cmops.c

Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83937
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jarried Lin 2024-08-16 10:24:18 +08:00 • committed by Felix Held
commit abf34584db
6 changed files with 39 additions and 28 deletions
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30
src/soc/mediatek/common/l2c_ops.c Normal file
View file

@ -0,0 +1,30 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <soc/mcucfg.h>
#include <soc/mmu_operations.h>
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
void mtk_soc_disable_l2c_sram(void)
{
unsigned long v;
SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
dsb();
__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
v |= (0xf << 4);
__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
dsb();
do {
__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
} while (((v >> 0x4) & 0xf) != 0xf);
SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
dsb();
}

29
src/soc/mediatek/common/mmu_cmops.c
View file

@ -1,34 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <soc/mcucfg.h>
#include <soc/mmu_operations.h>
#include <soc/symbols.h>
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
void mtk_soc_disable_l2c_sram(void)
{
unsigned long v;
SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
dsb();
__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
v |= (0xf << 4);
__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
dsb();
do {
__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
} while (((v >> 0x4) & 0xf) != 0xf);
SET32_BITFIELDS(&mtk_mcucfg->mp0_cluster_cfg0,
MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
dsb();
}
#include <soc/mmu_operations.h>
/* mtk_soc_after_dram is called in romstage */
void mtk_soc_after_dram(void)

2
src/soc/mediatek/mt8186/Makefile.mk
View file

@ -23,6 +23,7 @@ romstage-y += ../common/cbmem.c
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
romstage-y += ../common/emi.c
romstage-y += ../common/l2c_ops.c
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
@ -41,6 +42,7 @@ ramstage-y += ../common/dfd.c
ramstage-y += ../common/display.c
ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += ../common/emi.c
ramstage-y += ../common/l2c_ops.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c msdc.c

2
src/soc/mediatek/mt8188/Makefile.mk
View file

@ -21,6 +21,7 @@ romstage-y += ../common/clkbuf.c
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
romstage-y += ../common/emi.c
romstage-y += ../common/l2c_ops.c
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
@ -43,6 +44,7 @@ ramstage-y += ../common/dpm.c
ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += ../common/emi.c
ramstage-y += ../common/l2c_ops.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c

2
src/soc/mediatek/mt8192/Makefile.mk
View file

@ -21,6 +21,7 @@ romstage-y += ../common/cbmem.c
romstage-y += ../common/clkbuf.c srclken_rc.c
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
romstage-y += ../common/l2c_ops.c
romstage-y += ../common/memory.c ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
romstage-y += ../common/pll.c pll.c
@ -39,6 +40,7 @@ ramstage-y += devapc.c
ramstage-y += ../common/dfd.c
ramstage-y += ../common/dpm.c
ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += ../common/l2c_ops.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c

2
src/soc/mediatek/mt8195/Makefile.mk
View file

@ -23,6 +23,7 @@ romstage-y += ../common/clkbuf.c
romstage-y += ../common/dram_init.c
romstage-y += ../common/dramc_param.c
romstage-y += emi.c
romstage-y += ../common/l2c_ops.c
romstage-y += ../common/memory.c
romstage-y += ../common/memory_test.c
romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
@ -51,6 +52,7 @@ ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c
ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c
ramstage-y += emi.c
ramstage-y += hdmi.c
ramstage-y += ../common/l2c_ops.c
ramstage-y += ../common/mcu.c
ramstage-y += ../common/mcupm.c
ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c