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newconfig is no more.

Browse source 
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-02-07 21:43:48 +00:00
commit abf2ad716d
653 changed files with 15 additions and 64257 deletions
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228
src/mainboard/intel/d945gclf/Config.lb
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
##
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
##
##
## Only use the option table in a normal image
##
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
##
## Image size calculation
##
include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
driver rtl8168.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
if CONFIG_GENERATE_ACPI_TABLES
object fadt.o
object acpi_tables.o
makerule dsdt.c
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
action "mv $(CURDIR)/dsdt.hex dsdt.c"
end
object ./dsdt.o
end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/x86/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
mainboardinit cpu/intel/model_106cx/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
###
### O.k. We aren't just an intermediary anymore!
###
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/intel/i945
device apic_cluster 0 on
chip cpu/intel/socket_441
device apic 0 on end
end
end
device pci_domain 0 on
device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port
device pci 02.0 on end # vga controller
device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x07"
register "pirqc_routing" = "0x05"
register "pirqd_routing" = "0x07"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x06"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
register "gpe0_en" = "0x20000601"
register "ide_legacy_combined" = "0x1"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe
device pci 1c.1 on end # PCIe
device pci 1c.2 on end # PCIe
#device pci 1c.3 off end # PCIe port 4
#device pci 1c.4 off end # PCIe port 5
#device pci 1c.5 off end # PCIe port 6
device pci 1d.0 on end # USB UHCI
device pci 1d.1 on end # USB UHCI
device pci 1d.2 on end # USB UHCI
device pci 1d.3 on end # USB UHCI
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on end # PCI bridge
#device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47m15x
device pnp 2e.0 off # Floppy
end
device pnp 2e.3 off # Parport
end
device pnp 2e.4 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 on
io 0x60 = 0x2f8
irq 0x70 = 3
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
end
device pnp 2e.7 on # Keyboard+Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
irq 0xf0 = 0x82 # HW accel A20.
end
device pnp 2e.8 on # GAME
# all default
end
device pnp 2e.a on # PME
end
device pnp 2e.b on # MPU
end
end
end
#device pci 1f.1 off end # IDE
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
#device pci 1f.4 off end # Realtek ID Codec
end
end
end

329
src/mainboard/intel/d945gclf/Options.lb
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# Tables
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_GENERATE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_HAVE_MAINBOARD_RESOURCES
# SMP
uses CONFIG_SMP
uses CONFIG_LOGICAL_CPUS
uses CONFIG_AP_IN_SIPI_WAIT
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_IOAPIC
# Image Size
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
# Payload
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
# Build Internals
uses CONFIG_RAMBASE
uses CONFIG_ROMBASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_XIP_ROM_BASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_SMI_HANDLER
uses CONFIG_PCIE_CONFIGSPACE_HOLE
uses CONFIG_MMCONF_SUPPORT
uses CONFIG_MMCONF_BASE_ADDRESS
uses CONFIG_GFXUMA
#
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
# Timers
uses CONFIG_UDELAY_LAPIC
# Console
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN
uses CONFIG_DEBUG
# Toolchain
uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
# Tweaks
uses CONFIG_GDB_STUB
uses CONFIG_MAX_REBOOT_CNT
uses CONFIG_USE_WATCHDOG_ON_BOOT
uses COREBOOT_EXTRA_VERSION
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
###
### Build options
###
##
##
default CONFIG_MAX_REBOOT_CNT=3
##
## Use the watchdog to break out of a lockup condition
##
default CONFIG_USE_WATCHDOG_ON_BOOT=0
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE=CONFIG_FALLBACK_SIZE*2
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
##
default CONFIG_UDELAY_LAPIC=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build SMI handler
##
default CONFIG_HAVE_SMI_HANDLER=1
##
## Leave a hole for mmapped PCIe config space
##
default CONFIG_PCIE_CONFIGSPACE_HOLE=1
default CONFIG_MMCONF_SUPPORT=1
default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
##
## UMA
##
default CONFIG_GFXUMA=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=18
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code to provide ACPI support
##
default CONFIG_GENERATE_ACPI_TABLES=1
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
default CONFIG_HAVE_ACPI_RESUME=1
##
## Build code to export a CMOS option table
##
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
##
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
#VGA Console
default CONFIG_CONSOLE_VGA=1
# There are some network option roms that don't work with
# coreboot's x86emu. Thus, we only execute the VGA option rom
# for now:
default CONFIG_VGA_ROM_RUN=1
default CONFIG_PCI_ROM_RUN=0
default CONFIG_DEBUG=0
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
default CONFIG_AP_IN_SIPI_WAIT=1
##
## enable CACHE_AS_RAM specifics
##
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_SIZE=0x8000
default CONFIG_DCACHE_RAM_BASE=0xffed8000
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Execute In Place settings
##
default CONFIG_XIP_ROM_SIZE = 128 * 1024
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
default CONFIG_MAINBOARD_VENDOR= "INTEL"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x464c
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 0xb800
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00100000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD=1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end

212
src/mainboard/intel/eagleheights/Config.lb
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@ -1,212 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##
##
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
##
##
## Only use the option table in a normal image
##
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
if CONFIG_GENERATE_ACPI_TABLES
object fadt.o
object acpi_tables.o
makerule dsdt.c
depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
action "mv $(CURDIR)/dsdt.hex dsdt.c"
end
object ./dsdt.o
end
if CONFIG_HAVE_HARD_RESET object reset.o end
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
end
else
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/x86/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
###
### O.k. We aren't just an intermediary anymore!
###
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/intel/i3100
device pci_domain 0 on
device pci 00.0 on end # IMCH
device pci 00.1 on end # IMCH error status
device pci 01.0 on end # IMCH EDMA engine
device pci 02.0 on end # PCIe port A/A0
device pci 03.0 on end # PCIe port A1
chip southbridge/intel/i3100
# PIRQ line -> legacy IRQ mappings
register "pirq_a_d" = "0x8b808a8a"
register "pirq_e_h" = "0x85808080"
device pci 1c.0 on end # PCIe port B0
device pci 1c.1 off end # PCIe port B1
device pci 1c.2 off end # PCIe port B2
device pci 1c.3 off end # PCIe port B3
device pci 1d.0 on end # USB (UHCI) 1
device pci 1d.1 on end # USB (UHCI) 2
device pci 1d.7 on end # USB (EHCI)
device pci 1e.0 on end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/intel/i3100
device pnp 4e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end
chip superio/smsc/smscsuperio
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.2 off # Serial Port 4
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.3 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 2
end
device pnp 2e.4 off # Serial Port 3
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 2e.7 on # PS/2 Keyboard / Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
device pnp 2e.a off # Runtime registers
io 0x60 = 0x600
end
end
end
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
device pci 1f.4 on end # Performance counters
end
end
device apic_cluster 0 on
chip cpu/intel/bga956
device apic 0 on end
end
end
end

323
src/mainboard/intel/eagleheights/Options.lb
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@ -1,323 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##
# Tables
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_GENERATE_ACPI_TABLES
uses CONFIG_HAVE_MAINBOARD_RESOURCES
# SMP
uses CONFIG_SMP
uses CONFIG_LOGICAL_CPUS
uses CONFIG_AP_IN_SIPI_WAIT
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_IOAPIC
# Image Size
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
# Payload
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_PRECOMPRESSED_PAYLOAD
# Build Internals
uses CONFIG_RAMBASE
uses CONFIG_ROMBASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_XIP_ROM_BASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_HAVE_SMI_HANDLER
uses CONFIG_PCIE_CONFIGSPACE_HOLE
uses CONFIG_MMCONF_SUPPORT
uses CONFIG_MMCONF_BASE_ADDRESS
#
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
# Timers
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
# Console
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_VGA
uses CONFIG_VGA_ROM_RUN
uses CONFIG_PCI_ROM_RUN
uses CONFIG_DEBUG
uses CONFIG_VGA
uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
# Toolchain
uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
# Tweaks
uses CONFIG_GDB_STUB
uses CONFIG_MAX_REBOOT_CNT
uses CONFIG_USE_WATCHDOG_ON_BOOT
uses COREBOOT_EXTRA_VERSION
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
###
### Build options
###
##
##
default CONFIG_MAX_REBOOT_CNT=3
##
## Use the watchdog to break out of a lockup condition
##
default CONFIG_USE_WATCHDOG_ON_BOOT=0
##
## ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE=1024*1024
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
## Use timer2
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build SMI handler
##
default CONFIG_HAVE_SMI_HANDLER=0
##
## Leave a hole for mmapped PCIe config space
##
default CONFIG_PCIE_CONFIGSPACE_HOLE=1
default CONFIG_MMCONF_SUPPORT=1
default CONFIG_MMCONF_BASE_ADDRESS=0xE0000000
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code to provide ACPI support
##
default CONFIG_GENERATE_ACPI_TABLES=1
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
##
## Build code to export a CMOS option table
##
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
#VGA Console
default CONFIG_CONSOLE_VGA=0
# There are some network option roms that don't work with
# coreboot's x86emu. Thus, we only execute the VGA option rom
# for now:
default CONFIG_VGA_ROM_RUN=0
default CONFIG_PCI_ROM_RUN=0
default CONFIG_DEBUG=0
#default CONFIG_VGA=0
#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
default CONFIG_AP_IN_SIPI_WAIT=1
##
## enable CACHE_AS_RAM specifics
##
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_SIZE=0x8000
default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
default CONFIG_USE_PRINTK_IN_CAR=1
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="EagleHeights"
default CONFIG_MAINBOARD_VENDOR= "Intel"
###
### coreboot layout values
###
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00100000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD=1
default CONFIG_PRECOMPRESSED_PAYLOAD=1
default CONFIG_COMPRESSED_PAYLOAD_LZMA=1
#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end

182
src/mainboard/intel/jarrell/Config.lb
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@ -1,182 +0,0 @@
##
## Only use the option table in a normal image
##
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
if CONFIG_HAVE_HARD_RESET object reset.o end
##
## Romcc output
##
makerule ./failover.E
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu_enable.inc
mainboardinit cpu/x86/sse_enable.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse_disable.inc
mainboardinit cpu/x86/mmx_disable.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/intel/e7520
device pci_domain 0 on
device pci 00.0 on end
device pci 00.1 on end
device pci 01.0 on end
device pci 02.0 on
chip southbridge/intel/pxhd # pxhd1
device pci 00.0 on end
device pci 00.1 on end
device pci 00.2 on
chip drivers/generic/generic
device pci 04.0 on end
device pci 04.1 on end
end
end
device pci 00.3 on end
end
end
device pci 06.0 on end
chip southbridge/intel/i82801er # i82801er
device pci 1d.0 on end
device pci 1d.1 on end
device pci 1d.2 on end
device pci 1d.3 off end
device pci 1d.7 on end
device pci 1e.0 on
chip drivers/ati/ragexl
device pci 0c.0 on end
end
end
device pci 1f.0 on
chip superio/nsc/pc87427
device pnp 2e.0 off end
device pnp 2e.2 on
# io 0x60 = 0x2f8
# irq 0x70 = 3
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on
# io 0x60 = 0x3f8
# irq 0x70 = 4
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.4 off end
device pnp 2e.5 off end
device pnp 2e.6 on
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end
device pnp 2e.9 off end
device pnp 2e.a off end
device pnp 2e.f on end
device pnp 2e.10 off end
device pnp 2e.14 off end
end
end
device pci 1f.1 on end
device pci 1f.2 off end
device pci 1f.3 on end
device pci 1f.5 off end
device pci 1f.6 off end
register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
end
end
device apic_cluster 0 on
chip cpu/intel/socket_mPGA604 # cpu 0
device apic 0 on end
end
chip cpu/intel/socket_mPGA604 # cpu 1
device apic 6 on end
end
end
end

242
src/mainboard/intel/jarrell/Options.lb
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@ -1,242 +0,0 @@
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
uses CONFIG_MAX_REBOOT_CNT
uses CONFIG_USE_WATCHDOG_ON_BOOT
###
### Build options
###
##
## Because we do the stutter start we need more attempts
##
default CONFIG_MAX_REBOOT_CNT=8
##
## Use the watchdog to break out of a lockup condition
##
default CONFIG_USE_WATCHDOG_ON_BOOT=1
##
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE=2097152
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
## Use timer2
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=18
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_LOGICAL_CPUS=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="SE7520JR22D"
default CONFIG_MAINBOARD_VENDOR= "Intel"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1079
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3437
###
### coreboot layout values
###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## Coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD=1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
##
default CONFIG_CONSOLE_BTEXT=0
### End Options.lb
end

160
src/mainboard/intel/mtarvon/Config.lb
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@ -1,160 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
##
## Romcc output
##
makerule ./failover.E
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu_enable.inc
mainboardinit cpu/x86/sse_enable.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse_disable.inc
mainboardinit cpu/x86/mmx_disable.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/intel/i3100
device pci_domain 0 on
device pci 00.0 on end # IMCH
device pci 00.1 on end # IMCH error status
device pci 01.0 on end # IMCH EDMA engine
device pci 02.0 on end # PCIe port A/A0
device pci 03.0 on end # PCIe port A1
chip southbridge/intel/i3100
# PIRQ line -> legacy IRQ mappings
register "pirq_a_d" = "0x0b070a05"
register "pirq_e_h" = "0x0a808080"
device pci 1c.0 on end # PCIe port B0
device pci 1c.1 on end # PCIe port B1
device pci 1c.2 on end # PCIe port B2
device pci 1c.3 on end # PCIe port B3
device pci 1d.0 on end # USB (UHCI) 1
device pci 1d.1 on end # USB (UHCI) 2
device pci 1d.7 on end # USB (EHCI)
device pci 1e.0 on end # PCI bridge
device pci 1e.2 on end # audio
device pci 1e.3 on end # modem
device pci 1f.0 on # LPC bridge
chip superio/intel/i3100
device pnp 4e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end
end
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
end
end
device apic_cluster 0 on
chip cpu/intel/socket_mPGA479M
device apic 0 on end
end
end
end

225
src/mainboard/intel/mtarvon/Options.lb
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@ -1,225 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
###
### Build options
###
##
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE = 2 * 1024 * 1024
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
## Use timer2
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=1
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_LOGICAL_CPUS=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="Mt. Arvon"
default CONFIG_MAINBOARD_VENDOR= "Intel"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
###
### Coreboot layout values
###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD=1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end

170
src/mainboard/intel/truxton/Config.lb
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@ -1,170 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
##
## Set all of the defaults for an x86 architecture
##
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
##
## Romcc output
##
makerule ./failover.E
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./failover.inc
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
end
makerule ./auto.E
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu_enable.inc
mainboardinit cpu/x86/sse_enable.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse_disable.inc
mainboardinit cpu/x86/mmx_disable.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
chip northbridge/intel/i3100
device pci_domain 0 on
device pci 00.0 on end # IMCH
device pci 00.1 on end # IMCH error status
device pci 01.0 on end # IMCH EDMA engine
device pci 02.0 on end # PCIe port A/A0
device pci 03.0 on end # PCIe port A1
device pci 04.0 on end # ?
device pci 08.0 off end # must be off to boot
device pci 0d.0 off end # must be off to boot
device pci 0d.1 off end # must be off to boot
chip southbridge/intel/i3100
# PIRQ line -> legacy IRQ mappings
register "pirq_a_d" = "0x0b070a05"
register "pirq_e_h" = "0x0a808080"
device pci 1d.0 on end # USB (UHCI)
device pci 1d.7 on end # USB (EHCI)
device pci 1f.0 on # LPC bridge
chip superio/intel/i3100
device pnp 4e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end
chip superio/smsc/smscsuperio
device pnp 2e.0 off end
device pnp 2e.3 off end
device pnp 2e.4 off end
device pnp 2e.5 off end
device pnp 2e.7 on # PS/2 keyboard / mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # PS/2 keyboard interrupt
irq 0x72 = 12 # PS/2 mouse interrupt
end
device pnp 2e.a off end
end
end
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus
device pci 1f.4 on end # ?
end
end
device apic_cluster 0 on
chip cpu/intel/ep80579
device apic 0 on end
end
end
end

236
src/mainboard/intel/truxton/Options.lb
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@ -1,236 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Arastra, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License version 2 as
## published by the Free Software Foundation.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_RAMTOP
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CC
uses HOSTCC
uses CONFIG_CROSS_COMPILE
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
###
### Build options
###
##
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE = 2 * 1024 * 1024
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
## Use timer2
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=1
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_LOGICAL_CPUS=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="Truxton"
default CONFIG_MAINBOARD_VENDOR= "Intel"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2680
###
### Coreboot layout values
###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00100000
##
## in order to have coreboot running at 0x100000, RAMTOP has to be set
##
default CONFIG_RAMTOP = 2*1024*1024
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD=1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
# Enable the VGA console.
default CONFIG_CONSOLE_VGA=1
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=5
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end

174
src/mainboard/intel/xe7501devkit/Config.lb
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@ -1,174 +0,0 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o end
if CONFIG_HAVE_HARD_RESET object reset.o end
##
## Romcc output
##
makerule ./failover.E
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_HAVE_FALLBACK_BOOT
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
else
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
end
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
mainboardinit cpu/x86/fpu_enable.inc
mainboardinit cpu/x86/sse_enable.inc
mainboardinit ./auto.inc
mainboardinit cpu/x86/sse_disable.inc
mainboardinit cpu/x86/mmx_disable.inc
##
## Include the secondary Configuration files
##
dir /pc80
config chip.h
# based on sample config for tyan/s2735
chip northbridge/intel/e7501
device pci_domain 0 on
device pci 0.0 on end # Chipset host controller
device pci 0.1 on end # Host RASUM controller
device pci 2.0 on # Hub interface B
chip southbridge/intel/i82870 # P64H2
device pci 1c.0 on end # IOAPIC - bus B
device pci 1d.0 on end # Hub to PCI-B bridge
device pci 1e.0 on end # IOAPIC - bus A
device pci 1f.0 on end # Hub to PCI-A bridge
end
end
device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
device pci 4.0 on # Hub interface D
chip southbridge/intel/i82870 # P64H2
device pci 1c.0 on end # IOAPIC - bus B
device pci 1d.0 on end # Hub to PCI-B bridge
device pci 1e.0 on end # IOAPIC - bus A
device pci 1f.0 on end # Hub to PCI-A bridge
end
end
device pci 6.0 on end # E7501 Power management registers? (undocumented)
chip southbridge/intel/i82801ca
device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
device pci 1d.1 off end # USB (not populated)
device pci 1d.2 off end # USB (not populated)
device pci 1e.0 on # Hub to PCI bridge
device pci 0.0 on end
end
device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47b272
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.3 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1 # Keyboard interrupt
irq 0x72 = 12 # Mouse interrupt
end
device pnp 2e.a off end # ACPI
end
end
device pci 1f.1 on end # IDE
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # AC97 Audio
device pci 1f.6 off end # AC97 Modem
end # SB
end # PCI_DOMAIN
device apic_cluster 0 on
chip cpu/intel/socket_mPGA604
device apic 0 on end
end
chip cpu/intel/socket_mPGA604
device apic 6 on end
end
end
end

238
src/mainboard/intel/xe7501devkit/Options.lb
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@ -1,238 +0,0 @@
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_MAX_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_DEBUG
#uses CONFIG_CPU_OPT
## These are defined in target Config.lb, don't add here
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_FALLBACK_SIZE
uses COREBOOT_EXTRA_VERSION
## These are defined in mainboard Config.lb, don't add here
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_HAVE_HARD_RESET
default CONFIG_HAVE_HARD_RESET = 1
###
### Build options
###
##
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE=2097152
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Build code for the fallback boot?
##
default CONFIG_HAVE_FALLBACK_BOOT=1
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
## Delay timer options
##
default CONFIG_UDELAY_TSC=1
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=12
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
## Build code to export ACPI tables?
default CONFIG_GENERATE_ACPI_TABLES=1
##
## Build code to export a CMOS option table?
##
default CONFIG_HAVE_OPTION_TABLE=0
## CMOS checksum definitions (units == bytes)
## These must match the checksum record in cmos.layout
default CONFIG_LB_CKS_RANGE_START=128
default CONFIG_LB_CKS_RANGE_END=130
default CONFIG_LB_CKS_LOC=131
##
## Build code for SMP support
## Only worry about 2 micro processors
## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=2
default CONFIG_LOGICAL_CPUS=0
default CONFIG_MAX_PHYSICAL_CPUS=2
# VGA Console
# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
# to VGA.rom
default CONFIG_CONSOLE_VGA=0
default CONFIG_PCI_ROM_RUN=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Motherboard identification
##
default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
default CONFIG_MAINBOARD_VENDOR="Intel"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
###
### coreboot layout values
###
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default CONFIG_HEAP_SIZE=0x4000
##
## CMOS settings not currently supported due to conflicts with factory BIOS
##
default CONFIG_USE_OPTION_TABLE = 0
##
## Coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
default CONFIG_DEBUG=1
# default CONFIG_CPU_OPT="-g"
### End Options.lb
end