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newconfig is no more.

Browse source 
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-02-07 21:43:48 +00:00
commit abf2ad716d
653 changed files with 15 additions and 64257 deletions
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235
src/mainboard/broadcom/blast/Config.lb
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@ -1,235 +0,0 @@
## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
##
## Build the objects we have code for in this directory.
##
driver mainboard.o
#dir /drivers/si/3114
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE
object get_bus_conf.o
object irq_tables.o
end
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./cache_as_ram_auto.inc
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
mainboardinit cpu/x86/32bit/reset32.inc
ldscript /cpu/x86/32bit/reset32.lds
end
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
###
### O.k. We aren't just an intermediary anymore!
###
##
## Setup RAM
##
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
##
## Include the secondary Configuration files
##
config chip.h
# sample config for broadcom/blast
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
chip cpu/amd/socket_940
device apic 0 on end
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0
chip southbridge/broadcom/bcm5780 # HT2000
device pci 0.0 on end # PXB 1 0x0130
device pci 1.0 on # PXB 2 0x0130
device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
end
device pci 2.0 on end # PCI E 1 #0x0132
device pci 3.0 on end # PCI E 2
device pci 4.0 on end # PCI E 3
device pci 5.0 on end # PCI E 4
end
chip southbridge/broadcom/bcm5785 # HT1000
device pci 0.0 on # HT PXB 0x0036
device pci d.0 on end # PPBX 0x0104
device pci e.0 on end # SATA 0x024a
end
device pci 1.0 on # Legacy pci main 0x0205
chip drivers/i2c/i2cmux2 # pca9554 smbus mux
device i2c 71 on end #0 pca9554 0
device i2c 71 on end #0 pca9554 1
device i2c 71 on end #0 pca9554 2
device i2c 71 on end #0 pca9554 3
device i2c 71 on end #0 pca9554 4
device i2c 71 on end #0 pca9554 5
device i2c 71 on #0 pca9554 6
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end
end
end
device i2c 71 on #1 pca9554 7
chip drivers/generic/generic #dimm 1-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 1-0-1
device i2c 51 on end
end
chip drivers/generic/generic #dimm 1-1-0
device i2c 52 on end
end
chip drivers/generic/generic #dimm 1-1-1
device i2c 53 on end
end
end
end
end
device pci 1.1 on end # IDE 0x0214
device pci 1.2 on # LPC 0x0234
chip superio/nsc/pc87417
device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.2 off # Com 2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on # Com 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.4 off end # SWC
device pnp 2e.5 off end # Mouse
device pnp 2e.6 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.7 off end # GPIO
device pnp 2e.f off end # XBUS
device pnp 2e.10 on #RTC
io 0x60 = 0x70
io 0x62 = 0x72
end
end
end
device pci 1.3 on end # WDTimer 0x0238
device pci 1.4 on end # XIOAPIC0 0x0235
device pci 1.5 on end # XIOAPIC1
device pci 1.6 on end # XIOAPIC2
device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB
device pci 2.2 on end # USB
device pci 4.0 on end # it is in bcm5785_0 bus
end
end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
end #pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid
# device pnp 0.4 off end # smbus_regs_all
# device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# end
end

260
src/mainboard/broadcom/blast/Options.lb
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@ -1,260 +0,0 @@
uses CONFIG_GENERATE_MP_TABLE
uses CONFIG_GENERATE_PIRQ_TABLE
uses CONFIG_GENERATE_ACPI_TABLES
uses CONFIG_HAVE_ACPI_RESUME
uses CONFIG_USE_FALLBACK_IMAGE
uses CONFIG_HAVE_FALLBACK_BOOT
uses CONFIG_HAVE_HARD_RESET
uses CONFIG_IRQ_SLOT_COUNT
uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses CONFIG_FALLBACK_SIZE
uses CONFIG_ROM_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_IMAGE_SIZE
uses CONFIG_ROM_SECTION_SIZE
uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses CONFIG_ROMBASE
uses CONFIG_XIP_ROM_SIZE
uses CONFIG_XIP_ROM_BASE
uses CONFIG_STACK_SIZE
uses CONFIG_HEAP_SIZE
uses CONFIG_USE_OPTION_TABLE
uses CONFIG_LB_CKS_RANGE_START
uses CONFIG_LB_CKS_RANGE_END
uses CONFIG_LB_CKS_LOC
uses CONFIG_MAINBOARD_PART_NUMBER
uses CONFIG_MAINBOARD_VENDOR
uses CONFIG_MAINBOARD
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_RAMBASE
uses CONFIG_TTYS0_BAUD
uses CONFIG_TTYS0_BASE
uses CONFIG_TTYS0_LCS
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
uses CONFIG_CROSS_COMPILE
uses CC
uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
uses CONFIG_SB_HT_CHAIN_ON_BUS0
uses CONFIG_USE_DCACHE_RAM
uses CONFIG_DCACHE_RAM_BASE
uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
###
### Build options
###
##
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
default CONFIG_ROM_SIZE=524288
##
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
## Build code for the fallback boot
##
default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
default CONFIG_GENERATE_PIRQ_TABLE=1
default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
default CONFIG_GENERATE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
default CONFIG_LB_CKS_RANGE_START=49
default CONFIG_LB_CKS_RANGE_END=122
default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
#default CONFIG_CONSOLE_VGA=1
#default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset
default CONFIG_HT_CHAIN_UNITID_BASE=0x6
#real SB Unit ID
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
#make the SB HT chain on bus 0
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
##
## enable CACHE_AS_RAM specifics
##
default CONFIG_USE_DCACHE_RAM=1
default CONFIG_DCACHE_RAM_BASE=0xcf000
default CONFIG_DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
default CONFIG_MAINBOARD_PART_NUMBER="blast"
default CONFIG_MAINBOARD_VENDOR="Broadcom"
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
###
### coreboot layout values
###
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
##
## Coreboot C code runs at this location in RAM
##
default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
##
default CONFIG_ROM_PAYLOAD = 1
###
### Defaults of options that you may want to override in the target config file
###
##
## The default compiler
##
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Disable the gdb stub by default
##
default CONFIG_GDB_STUB=0
default CONFIG_USE_PRINTK_IN_CAR=1
##
## The Serial Console
##
# To Enable the Serial Console
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default CONFIG_TTYS0_BAUD=115200
#default CONFIG_TTYS0_BAUD=57600
#default CONFIG_TTYS0_BAUD=38400
#default CONFIG_TTYS0_BAUD=19200
#default CONFIG_TTYS0_BAUD=9600
#default CONFIG_TTYS0_BAUD=4800
#default CONFIG_TTYS0_BAUD=2400
#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
##
## EMERG 1 system is unusable
## ALERT 2 action must be taken immediately
## CRIT 3 critical conditions
## ERR 4 error conditions
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
end