newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
parent
389240f288
commit
abf2ad716d
653 changed files with 15 additions and 64257 deletions
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 128 * 1024
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include /config/nofailovercalculation.lb
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default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
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arch i386 end
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driver mainboard.o
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if CONFIG_GENERATE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu_enable.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx_disable.inc
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dir /pc80
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config chip.h
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.6 on # Consumer IR
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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@ -1,97 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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uses CONFIG_GENERATE_MP_TABLE
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uses CONFIG_GENERATE_PIRQ_TABLE
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uses CONFIG_USE_FALLBACK_IMAGE
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uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_ARCH
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_SECTION_OFFSET
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_ROMBASE
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uses CONFIG_RAMBASE
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uses CONFIG_XIP_ROM_SIZE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_GENERATE_MP_TABLE
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_TTYS0_BAUD
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uses CONFIG_TTYS0_BASE
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uses CONFIG_TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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default CONFIG_ROM_SIZE = 256 * 1024
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default CONFIG_HAVE_FALLBACK_BOOT = 1
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default CONFIG_GENERATE_MP_TABLE = 0
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default CONFIG_HAVE_HARD_RESET = 0
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default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default CONFIG_GENERATE_PIRQ_TABLE = 1
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default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
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default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
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default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
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default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
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default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
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default CONFIG_STACK_SIZE = 8 * 1024
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default CONFIG_HEAP_SIZE = 16 * 1024
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default CONFIG_HAVE_OPTION_TABLE = 0
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#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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default CONFIG_USE_OPTION_TABLE = 0
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default CONFIG_RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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default CONFIG_CROSS_COMPILE = ""
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default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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default CONFIG_CONSOLE_SERIAL8250 = 1
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default CONFIG_TTYS0_BAUD = 115200
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default CONFIG_TTYS0_BASE = 0x3f8
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default CONFIG_TTYS0_LCS = 0x3 # 8n1
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
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default CONFIG_CONSOLE_VGA = 1
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default CONFIG_PCI_ROM_RUN = 1
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end
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@ -1,142 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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||||
## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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default CONFIG_XIP_ROM_SIZE = 128 * 1024
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include /config/nofailovercalculation.lb
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default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
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arch i386 end
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driver mainboard.o
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if CONFIG_GENERATE_PIRQ_TABLE
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object irq_tables.o
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end
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
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action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
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end
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makerule ./auto.E
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
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action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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if CONFIG_USE_FALLBACK_IMAGE
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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else
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mainboardinit cpu/x86/32bit/reset32.inc
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ldscript /cpu/x86/32bit/reset32.lds
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end
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mainboardinit arch/i386/lib/cpu_reset.inc
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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if CONFIG_USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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mainboardinit cpu/x86/fpu_enable.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/x86/mmx_disable.inc
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dir /pc80
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config chip.h
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chip northbridge/intel/i440bx # Northbridge
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device apic_cluster 0 on # APIC cluster
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chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
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device apic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/winbond/w83627hf # Super I/O
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.6 on # Consumer IR
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io 0x60 = 0x00
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end
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device pnp 3f0.7 on # Game port / MIDI / GPIO 1
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io 0x60 = 0x201
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io 0x62 = 0x330
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irq 0x70 = 9
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end
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device pnp 3f0.8 off # GPIO 2 / WDT
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end
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device pnp 3f0.9 off # GPIO 3
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end
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device pnp 3f0.a off # ACPI
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||||
end
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device pnp 3f0.b off # HWM (TODO)
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end
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||||
end
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||||
end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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device pci c.0 on end # Onboard audio (ES1371)
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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||||
end
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||||
end
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@ -1,97 +0,0 @@
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##
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||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
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||||
uses CONFIG_GENERATE_PIRQ_TABLE
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uses CONFIG_USE_FALLBACK_IMAGE
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||||
uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_ARCH
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 7.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # Consumer IR
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 7.1 on end # IDE, UDMA/33 (part of 82371EB)
|
||||
device pci 7.2 on end # USB
|
||||
device pci 7.3 on end # ACPI
|
||||
device pci 13.0 on end # IDE, UDMA/66 (HPT366 controller)
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
register "ide0_drive0_udma33_enable" = "1"
|
||||
register "ide0_drive1_udma33_enable" = "1"
|
||||
register "ide1_drive0_udma33_enable" = "1"
|
||||
register "ide1_drive1_udma33_enable" = "1"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 9 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb.
|
||||
|
||||
end
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/winbond/w83977f # SUper I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.4 on # RTC / On-Now control
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # IR
|
||||
# TODO?
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
# TODO?
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
# TODO?
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio (onboard)
|
||||
device pci 12.4 on end # VGA
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/model_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_SPLASH_GRAPHIC
|
||||
uses CONFIG_GX1_VIDEO
|
||||
uses CONFIG_GX1_VIDEOMODE
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
|
||||
## We want to support up to 1024x768@16 so we need 2MiB video memory.
|
||||
## Note: Higher resolutions might need faster SDRAM speed.
|
||||
default CONFIG_GX1_VIDEO = 1
|
||||
default CONFIG_GX1_VIDEOMODE = 0
|
||||
default CONFIG_SPLASH_GRAPHIC = 1
|
||||
default CONFIG_VIDEO_MB = 2
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 2 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
|
||||
end
|
||||
|
|
@ -1,152 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
|
||||
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end # Northbridge
|
||||
device pci 1.1 on end # Graphics
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
|
||||
register "lpc_serirq_enable" = "0x0000105a"
|
||||
register "lpc_serirq_polarity" = "0x0000EFA5"
|
||||
register "lpc_serirq_mode" = "1"
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "1" # 0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci d.0 on end # Ethernet
|
||||
device pci e.0 on end # Slot1
|
||||
device pci f.0 on # ISA Bridge
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off end # Com2
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GAME_MIDI_GIPO1
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b off end # HW Monitor
|
||||
end
|
||||
end
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
default CONFIG_CONSOLE_VGA=0
|
||||
default CONFIG_VIDEO_MB=8
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=4
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 32768
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,258 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object get_bus_conf.o
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
object fadt.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
|
||||
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
|
||||
action "mv dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
#The variables belong to mainboard are defined here.
|
||||
|
||||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_S1G1
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge
|
||||
chip southbridge/amd/rs690
|
||||
device pci 0.0 on end # HT 0x7910
|
||||
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
|
||||
device pci 5.0 on end # Internal Graphics 0x791F
|
||||
end
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x791b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x7914
|
||||
device pci 5.0 on end # PCIE P2P bridge 0x7915
|
||||
device pci 6.0 on end # PCIE P2P bridge 0x7916
|
||||
device pci 7.0 on end # PCIE P2P bridge 0x7917
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
register "gpp_configuration" = "4"
|
||||
register "port_enable" = "0xfc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 12.0 on end # SATA 0x4380
|
||||
device pci 13.0 on end # USB 0x4387
|
||||
device pci 13.1 on end # USB 0x4388
|
||||
device pci 13.2 on end # USB 0x4389
|
||||
device pci 13.3 on end # USB 0x438a
|
||||
device pci 13.4 on end # USB 0x438b
|
||||
device pci 13.5 on end # USB 2 0x4386
|
||||
device pci 14.0 on # SM 0x4385
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x438c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on # LPC 0x438d
|
||||
chip superio/ite/it8712f
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 off end # EC
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 off # GPIO, must be closed for unresolved reason.
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end #superio/ite/it8712f
|
||||
end #LPC
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # ACI 0x4382
|
||||
device pci 14.6 on end # MCI 0x438e
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "hda_viddid" = "0x10ec0882"
|
||||
end #southbridge/amd/sb600
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end #northbridge/amd/amdk8
|
||||
end #pci_domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
|
||||
|
|
@ -1,301 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VGA_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_GFXUMA
|
||||
uses CONFIG_HAVE_MAINBOARD_RESOURCES
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=1
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#1G memory hole
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
default CONFIG_VGA_ROM_RUN=1
|
||||
|
||||
# BTDC: Only one HT device on Herring.
|
||||
#HT Unit ID offset
|
||||
#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0x0
|
||||
|
||||
|
||||
#real SB Unit ID
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
|
||||
|
||||
#make the SB HT chain on bus 0
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="dbm690t"
|
||||
default CONFIG_MAINBOARD_VENDOR="amd"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
|
||||
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
##
|
||||
## coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_VIDEO_MB=1
|
||||
default CONFIG_GFXUMA=1
|
||||
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
|
||||
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end # Northbridge
|
||||
device pci 1.1 on end # Graphics
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
register "lpc_serirq_enable" = "0x00001002"
|
||||
register "lpc_serirq_polarity" = "0x0000EFFD"
|
||||
register "lpc_serirq_mode" = "1"
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" #0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "1"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci b.0 on end # Slot 3
|
||||
device pci c.0 on end # Slot 4
|
||||
device pci d.0 on end # Slot 1
|
||||
device pci e.0 on end # Slot 2
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
default CONFIG_CONSOLE_VGA=0
|
||||
default CONFIG_VIDEO_MB=8
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=6
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,218 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object get_bus_conf.o
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
object fadt.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
|
||||
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
|
||||
action "mv dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
#The variables belong to mainboard are defined here.
|
||||
|
||||
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
|
||||
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
|
||||
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
|
||||
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
|
||||
#Define gfx_dual_slot, 0: single slot, 1: dual slot
|
||||
#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
|
||||
#Define gfx_tmds, 0: didn't support TMDS, 1: support
|
||||
#Define gfx_compliance, 0: didn't support compliance, 1: support
|
||||
#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
|
||||
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # southbridge, K8 HT Configuration
|
||||
chip southbridge/amd/rs690
|
||||
device pci 0.0 on end # HT 0x7910
|
||||
# device pci 0.1 off end # CLK
|
||||
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
|
||||
device pci 5.0 on end # Internal Graphics 0x791F
|
||||
end
|
||||
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
|
||||
device pci 3.0 off end # PCIE P2P bridge 0x791b
|
||||
device pci 4.0 on end # PCIE P2P bridge 0x7914
|
||||
device pci 5.0 on end # PCIE P2P bridge 0x7915
|
||||
device pci 6.0 on end # PCIE P2P bridge 0x7916
|
||||
device pci 7.0 on end # PCIE P2P bridge 0x7917
|
||||
device pci 8.0 off end # NB/SB Link P2P bridge
|
||||
register "gpp_configuration" = "4"
|
||||
register "port_enable" = "0xfc"
|
||||
register "gfx_dev2_dev3" = "1"
|
||||
register "gfx_dual_slot" = "0"
|
||||
register "gfx_lane_reversal" = "0"
|
||||
register "gfx_tmds" = "0"
|
||||
register "gfx_compliance" = "0"
|
||||
register "gfx_reconfiguration" = "1"
|
||||
register "gfx_link_width" = "0"
|
||||
end
|
||||
chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
|
||||
device pci 12.0 on end # SATA 0x4380
|
||||
device pci 13.0 on end # USB 0x4387
|
||||
device pci 13.1 on end # USB 0x4388
|
||||
device pci 13.2 on end # USB 0x4389
|
||||
device pci 13.3 on end # USB 0x438a
|
||||
device pci 13.4 on end # USB 0x438b
|
||||
device pci 13.5 on end # USB 2 0x4386
|
||||
device pci 14.0 on # SM 0x4385
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 off end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 off end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 off end
|
||||
end
|
||||
end # SM
|
||||
device pci 14.1 on end # IDE 0x438c
|
||||
device pci 14.2 on end # HDA 0x4383
|
||||
device pci 14.3 on end # LPC 0x438d
|
||||
device pci 14.4 on end # PCI 0x4384
|
||||
device pci 14.5 on end # ACI 0x4382
|
||||
device pci 14.6 on end # MCI 0x438e
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "hda_viddid" = "0x10ec0882"
|
||||
end #southbridge/amd/sb600
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.1 on end # K8 Address Map
|
||||
device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode
|
||||
device pci 18.3 on end # K8 Miscellaneous Control
|
||||
end #northbridge/amd/amdk8
|
||||
end #pci_domain
|
||||
end #northbridge/amd/amdk8/root_complex
|
||||
|
||||
|
|
@ -1,301 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
##
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VGA_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_GFXUMA
|
||||
uses CONFIG_HAVE_MAINBOARD_RESOURCES
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=1
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#1G memory hole
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
default CONFIG_VGA_ROM_RUN=1
|
||||
|
||||
# BTDC: Only one HT device on Herring.
|
||||
#HT Unit ID offset
|
||||
#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0x0
|
||||
|
||||
|
||||
#real SB Unit ID
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
|
||||
|
||||
#make the SB HT chain on bus 0
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
|
||||
default CONFIG_MAINBOARD_VENDOR="amd"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
|
||||
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
##
|
||||
## coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_VIDEO_MB=1
|
||||
default CONFIG_GFXUMA=1
|
||||
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,115 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx2
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_gx2
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
register "lpc_serirq_enable" = "0x80" # enabled with default timing
|
||||
device pci d.0 on end # Realtek 8139 LAN
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.4 on end # UHCI
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=2
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,358 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/failovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE
|
||||
object mptable.o
|
||||
end
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
#if CONFIG_GENERATE_ACPI_TABLES
|
||||
# object acpi_tables.o
|
||||
# object fadt.o
|
||||
# if CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
# object dsdt_bus0.o
|
||||
# else
|
||||
# object dsdt.o
|
||||
# end
|
||||
# object ssdt.o
|
||||
# if CONFIG_ACPI_SSDTX_NUM
|
||||
# if CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
# object ssdt2_bus0.o
|
||||
# else
|
||||
# object ssdt2.o
|
||||
# end
|
||||
# end
|
||||
#end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
object fadt.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
|
||||
action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
|
||||
action "mv dsdt_lb.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
|
||||
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
|
||||
|
||||
if CONFIG_ACPI_SSDTX_NUM
|
||||
makerule ssdt2.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
|
||||
action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
|
||||
action "mv pci2.hex ssdt2.c"
|
||||
end
|
||||
object ./ssdt2.o
|
||||
makerule ssdt3.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
|
||||
action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
|
||||
action "mv pci3.hex ssdt3.c"
|
||||
end
|
||||
object ./ssdt3.o
|
||||
makerule ssdt4.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
|
||||
action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
|
||||
action "mv pci4.hex ssdt4.c"
|
||||
end
|
||||
object ./ssdt4.o
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
# compile cache_as_ram.c to auto.o
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
else
|
||||
if CONFIG_AP_CODE_IN_CAR
|
||||
makerule ./apc_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
|
||||
end
|
||||
ldscript /arch/i386/init/ldscript_apc.lb
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
# sample config for amd/serengeti_cheetah
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/amd/amd8132
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 off end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on
|
||||
chip drivers/i2c/i2cmux # pca9556 smbus mux
|
||||
device i2c 18 on #0 pca9516 1
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 18 on #1 pca9516 2
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # acpi
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on # northbridge
|
||||
chip southbridge/amd/amd8151
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 1.0 on end
|
||||
end
|
||||
end # device pci 19.0
|
||||
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
end
|
||||
|
||||
|
||||
end #pci_domain
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 off end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -1,325 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_FAILOVER_SIZE=0x01000
|
||||
|
||||
#more 1M for pgtbl
|
||||
default CONFIG_RAMTOP=2048*1024
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
## extra SSDT num
|
||||
default CONFIG_ACPI_SSDTX_NUM=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=8
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=4
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
default CONFIG_SERIAL_CPU_INIT=0
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=0
|
||||
default CONFIG_APIC_ID_OFFSET=0x8
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#Opteron K8 1G HT Support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0xa
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
|
||||
##
|
||||
## for rev F training on AP purpose
|
||||
##
|
||||
default CONFIG_AP_CODE_IN_CAR=1
|
||||
default CONFIG_MEM_TRAIN_SEQ=1
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT=1
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah"
|
||||
default CONFIG_MAINBOARD_VENDOR="AMD"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,362 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/failovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE
|
||||
object mptable.o
|
||||
end
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
object fadt.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
|
||||
action "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
|
||||
action "mv dsdt_lb.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
|
||||
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
|
||||
|
||||
if CONFIG_ACPI_SSDTX_NUM
|
||||
makerule ssdt2.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
|
||||
action "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
|
||||
action "mv pci2.hex ssdt2.c"
|
||||
end
|
||||
object ./ssdt2.o
|
||||
makerule ssdt3.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
|
||||
action "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
|
||||
action "mv pci3.hex ssdt3.c"
|
||||
end
|
||||
object ./ssdt3.o
|
||||
makerule ssdt4.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
|
||||
action "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
|
||||
action "mv pci4.hex ssdt4.c"
|
||||
end
|
||||
object ./ssdt4.o
|
||||
makerule ssdt5.c
|
||||
depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
|
||||
action "iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
|
||||
action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
|
||||
action "mv pci5.hex ssdt5.c"
|
||||
end
|
||||
object ./ssdt5.o
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
# compile cache_as_ram.c to auto.o
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
else
|
||||
if CONFIG_AP_CODE_IN_CAR
|
||||
makerule ./apc_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
|
||||
end
|
||||
ldscript /arch/i386/init/ldscript_apc.lb
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
dir /southbridge/amd/amd8151
|
||||
|
||||
# sample config for amd/serengeti_cheetah_fam10
|
||||
chip northbridge/amd/amdfam10/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_F_1207 #L1 and DDR2
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdfam10
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/amd/amd8132
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 off end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on
|
||||
chip drivers/i2c/i2cmux2 # pca9556 smbus mux
|
||||
chip drivers/i2c/i2cmux2 # pca9556 smbus mux
|
||||
device i2c 18 on #0 pca9516 1
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 18 on #1 pca9516 2
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # acpi
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
device pci 18.4 on end
|
||||
# device pci 00.5 on end
|
||||
end
|
||||
end #pci_domain
|
||||
#for node 32 to node 63
|
||||
# device pci_domain 0 on
|
||||
# chip northbridge/amd/amdfam10
|
||||
# device pci 00.0 on end# northbridge
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.0 on end
|
||||
# device pci 00.1 on end
|
||||
# device pci 00.2 on end
|
||||
# device pci 00.3 on end
|
||||
# device pci 00.4 on end
|
||||
# device pci 00.5 on end
|
||||
# end
|
||||
# end #pci_domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 off end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # hard reset
|
||||
# device pnp 0.9 off end # mcp55
|
||||
# device pnp 0.a on end # GH ext table
|
||||
# end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -1,365 +0,0 @@
|
|||
#
|
||||
# This file is part of the coreboot project.
|
||||
#
|
||||
# Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_PCI_BUS_SEGN_BITS
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_AMDMCT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_AMD_UCODE_PATCH_FILE
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=1024*1024
|
||||
|
||||
##
|
||||
##
|
||||
#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
||||
#FALLBACK: 1024K - 8K
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
#FAILOVER: 8k
|
||||
default CONFIG_FAILOVER_SIZE=0x02000
|
||||
|
||||
#more 1M for pgtbl
|
||||
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
|
||||
default CONFIG_RAMTOP=16384*1024
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
## extra SSDT num
|
||||
default CONFIG_ACPI_SSDTX_NUM=31
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=8
|
||||
default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#default CONFIG_SERIAL_CPU_INIT=0
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=1
|
||||
default CONFIG_APIC_ID_OFFSET=0x00
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0xa
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
#it only be 0, 1, 2, 3, 4 and default is 0
|
||||
#default CONFIG_PCI_BUS_SEGN_BITS=3
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc4000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x0c000
|
||||
#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
#default CONFIG_AP_CODE_IN_CAR=1
|
||||
default CONFIG_MEM_TRAIN_SEQ=2
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT=0
|
||||
|
||||
default CONFIG_AMDMCT = 1
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10"
|
||||
default CONFIG_MAINBOARD_VENDOR="AMD"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
|
||||
|
||||
##
|
||||
## Set microcode patch file name
|
||||
##
|
||||
## Barcelona rev DR-Ax: "mc_patch_01000020.h"
|
||||
## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
|
||||
## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
|
||||
## Shanghai rev DA-C2: "mc_patch_0100009f.h"
|
||||
##
|
||||
default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 768k heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0xc0000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00200000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,297 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
# config for arima/hdama
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/amd/amd8131
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on # PCIX bridge
|
||||
## On board NIC A
|
||||
#chip drivers/generic/generic
|
||||
# device pci 3.0 on
|
||||
# irq 0 = 0x13
|
||||
# end
|
||||
#end
|
||||
## On board NIC B
|
||||
#chip drivers/generic/generic
|
||||
# device pci 4.0 on
|
||||
# irq 0 = 0x13
|
||||
# end
|
||||
#end
|
||||
## PCI Slot 3
|
||||
#chip drivers/generic/generic
|
||||
# device pci 1.0 on
|
||||
# irq 0 = 0x11
|
||||
# irq 1 = 0x12
|
||||
# irq 2 = 0x13
|
||||
# irq 3 = 0x10
|
||||
# end
|
||||
#end
|
||||
## PCI Slot 4
|
||||
#chip drivers/generic/generic
|
||||
# device pci 2.0 on
|
||||
# irq 0 = 0x12
|
||||
# irq 1 = 0x13
|
||||
# irq 2 = 0x10
|
||||
# irq 3 = 0x11
|
||||
# end
|
||||
#end
|
||||
end
|
||||
device pci 0.1 on end # IOAPIC
|
||||
device pci 1.0 on # PCIX bridge
|
||||
## PCI Slot 1
|
||||
#chip drivers/generic/generic
|
||||
# device pci 1.0 on
|
||||
# irq 0 = 0x11
|
||||
# irq 1 = 0x12
|
||||
# irq 2 = 0x13
|
||||
# irq 3 = 0x10
|
||||
# end
|
||||
#end
|
||||
## PCI Slot 2
|
||||
#chip drivers/generic/generic
|
||||
# device pci 2.0 on
|
||||
# irq 0 = 0x12
|
||||
# irq 1 = 0x13
|
||||
# irq 2 = 0x10
|
||||
# irq 3 = 0x11
|
||||
# end
|
||||
#end
|
||||
end
|
||||
device pci 1.1 on end # IOAPIC
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent of the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end # USB0
|
||||
device pci 0.1 on end # USB1
|
||||
device pci 0.2 off end # USB 2.0
|
||||
device pci 1.0 off end # LAN
|
||||
device pci 6.0 on end # ATI Rage XL
|
||||
## PCI Slot 5 (correct?)
|
||||
#chip drivers/generic/generic
|
||||
# device pci 5.0 on
|
||||
# irq 0 = 0x11
|
||||
# irq 1 = 0x12
|
||||
# irq 2 = 0x13
|
||||
# irq 3 = 0x10
|
||||
# end
|
||||
#end
|
||||
## PCI Slot 6 (correct?)
|
||||
#chip drivers/generic/generic
|
||||
# device pci 4.0 on
|
||||
# irq 0 = 0x10
|
||||
# irq 1 = 0x11
|
||||
# irq 2 = 0x12
|
||||
# irq 3 = 0x13
|
||||
# end
|
||||
#end
|
||||
|
||||
end
|
||||
# LPC bridge
|
||||
device pci 1.0 on
|
||||
chip superio/nsc/pc87360
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # Mouse
|
||||
device pnp 2e.6 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # ACB
|
||||
device pnp 2e.9 off end # FSCM
|
||||
device pnp 2e.a off end # WDT
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end # IDE
|
||||
device pci 1.2 on end # SMBus 2.0
|
||||
device pci 1.3 on # System Management
|
||||
chip drivers/generic/generic
|
||||
#phillips pca9545 smbus mux
|
||||
device i2c 70 on
|
||||
# analog_devices adm1026
|
||||
chip drivers/generic/generic
|
||||
device i2c 2c on end
|
||||
end
|
||||
end
|
||||
device i2c 70 on end
|
||||
device i2c 70 on end
|
||||
device i2c 70 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end
|
||||
device pci 1.5 off end # AC97 Audio
|
||||
device pci 1.6 on end # AC97 Modem
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end # LDT1
|
||||
device pci 18.0 on end # LDT2
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # chip northbridge/amd/amdk8
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,242 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_LOGICAL_CPUS enables dual core support
|
||||
##
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=4
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xcf000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x1000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
#VGA
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
|
||||
default CONFIG_MAINBOARD_VENDOR="ARIMA"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
|
||||
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
|
||||
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end # Northbridge
|
||||
device pci 1.1 on end # Graphics
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
register "lpc_serirq_enable" = "0x00001002"
|
||||
register "lpc_serirq_polarity" = "0x0000EFFD"
|
||||
register "lpc_serirq_mode" = "1"
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" #0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x2F8"
|
||||
register "com1_irq" = "3"
|
||||
register "com2_enable" = "1"
|
||||
register "com2_address" = "0x3F8"
|
||||
register "com2_irq" = "4"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci b.0 on end # Slot 3
|
||||
device pci c.0 on end # Slot 4
|
||||
device pci d.0 on end # Slot 1
|
||||
device pci e.0 on end # Slot 2
|
||||
device pci f.0 on end # ISA Bridge
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
default CONFIG_CONSOLE_VGA=0
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
default CONFIG_VIDEO_MB=8
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=3
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
config chip.h
|
||||
driver vgabios.o
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 on end # Ethernet
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc87351 # Super I/O
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.e on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # System wake-up control (SWC)
|
||||
irq 0x60 = 0x500
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
irq 0x60 = 0x800
|
||||
end
|
||||
device pnp 2e.8 on # Fan speed control
|
||||
irq 0x60 = 0x900
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "0" # No connector on this board
|
||||
end
|
||||
end
|
||||
chip cpu/amd/model_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_SPLASH_GRAPHIC
|
||||
uses CONFIG_GX1_VIDEO
|
||||
uses CONFIG_GX1_VIDEOMODE
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
|
||||
## We want to support up to 1024x768@16 so we need 2MiB video memory.
|
||||
## Note: Higher resolutions might need faster SDRAM speed.
|
||||
default CONFIG_GX1_VIDEO = 1
|
||||
default CONFIG_GX1_VIDEOMODE = 0
|
||||
default CONFIG_SPLASH_GRAPHIC = 1
|
||||
default CONFIG_VIDEO_MB = 2
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 3 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
|
||||
end
|
||||
|
|
@ -1,146 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
# makerule ./failover.E
|
||||
# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
# action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
# end
|
||||
#
|
||||
# makerule ./failover.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
# action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
# end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
# if CONFIG_USE_FALLBACK_IMAGE
|
||||
# ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
# end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc87351 # Super I/O
|
||||
device pnp 2e.4 on # PS/2 keyboard (+ mouse?)
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
# irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.a on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.e on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.f off # Floppy
|
||||
io 0x60 = 0x3f2
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.10 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.12 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/model_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,163 +0,0 @@
|
|||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
# uses CONFIG_CONSOLE_VGA
|
||||
# uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=5
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
# default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
# default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
|
||||
# VGA Console
|
||||
# default CONFIG_CONSOLE_VGA=1
|
||||
# default CONFIG_PCI_ROM_RUN=1
|
||||
default CONFIG_VIDEO_MB = 0
|
||||
|
||||
end
|
||||
|
|
@ -1,241 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
|
||||
## (Thanks to LSRA University of Mannheim for their support)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/failovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
# Needed by irq_tables and mptable and acpi_tables.
|
||||
object get_bus_conf.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
# Include an ID string (for safe flashing).
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
# ROMSTRAP table for CK804.
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/nvidia/ck804/romstrap.inc
|
||||
ldscript /southbridge/nvidia/ck804/romstrap.lds
|
||||
end
|
||||
end
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_939 # Socket 939 CPU
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
|
||||
device pci_domain 0 on # PCI domain
|
||||
chip northbridge/amd/amdk8 # mc0
|
||||
device pci 18.0 on # Northbridge
|
||||
# Devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/ck804 # Southbridge
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/ite/it8712f # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2 (N/A on this board)
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.4 on # Environment controller
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x0000
|
||||
irq 0x70 = 0x00
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x71 = 2
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
irq 0x71 = 2
|
||||
end
|
||||
device pnp 2e.7 on # GPIO config
|
||||
io 0x60 = 0x0800
|
||||
# Set GPIO 1 & 2
|
||||
io 0x25 = 0x0000
|
||||
# Set GPIO 3 & 4
|
||||
io 0x27 = 0x2540
|
||||
# GPIO Polarity for Set 3
|
||||
io 0xb2 = 0x2100
|
||||
# GPIO Pin Internal Pull up for Set 3
|
||||
io 0xba = 0x0100
|
||||
# Simple I/O register config
|
||||
io 0xc0 = 0x0000
|
||||
io 0xc2 = 0x2540
|
||||
io 0xc8 = 0x0000
|
||||
io 0xca = 0x0500
|
||||
end
|
||||
device pnp 2e.8 on # Midi port
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 10
|
||||
end
|
||||
device pnp 2e.9 on # Game port
|
||||
io 0x60 = 0x201
|
||||
end
|
||||
device pnp 2e.a off # IR (N/A on this board)
|
||||
io 0x60 = 0x310
|
||||
irq 0x70 = 11
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
# chip drivers/generic/generic #dimm 0-0-0
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 0-0-1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 0-1-0
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 0-1-1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 1-0-0
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 1-0-1
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 1-1-0
|
||||
# device i2c 56 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #dimm 1-1-1
|
||||
# device i2c 57 on end
|
||||
# end
|
||||
end
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # Onboard audio (ACI)
|
||||
device pci 4.1 off end # Onboard modem (MCI), N/A
|
||||
device pci 6.0 on end # IDE
|
||||
device pci 7.0 on end # SATA 1
|
||||
device pci 8.0 on end # SATA 0
|
||||
device pci 9.0 on end # PCI
|
||||
device pci a.0 on end # NIC
|
||||
device pci b.0 on end # PCI E 3
|
||||
device pci c.0 on end # PCI E 2
|
||||
device pci d.0 on end # PCI E 1
|
||||
device pci e.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
# register "mac_eeprom_smbus" = "3"
|
||||
# register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,168 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
|
||||
## (Thanks to LSRA University of Mannheim for their support)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_CONSOLE_BTEXT
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
default CONFIG_ROM_SIZE = 512 * 1024
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_FAILOVER_SIZE = 4 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 13
|
||||
default CONFIG_GENERATE_MP_TABLE = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 1
|
||||
# Move the default coreboot CMOS range off of AMD RTC registers.
|
||||
default CONFIG_LB_CKS_RANGE_START = 49
|
||||
default CONFIG_LB_CKS_RANGE_END = 122
|
||||
default CONFIG_LB_CKS_LOC = 123
|
||||
# SMP support (only worry about 2 micro processors).
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_MAX_CPUS = 2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS = 1
|
||||
default CONFIG_LOGICAL_CPUS = 1
|
||||
# 1G memory hole.
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
|
||||
# HT Unit ID offset, default is 1, the typical one.
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE = 0
|
||||
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
|
||||
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10
|
||||
# Make the SB HT chain on bus 0, default is not (0).
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
|
||||
# Only offset for SB chain?, default is yes(1).
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
|
||||
# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console
|
||||
default CONFIG_CONSOLE_VGA = 1 # For VGA console
|
||||
default CONFIG_PCI_ROM_RUN = 1 # For VGA console
|
||||
default CONFIG_USE_DCACHE_RAM = 1
|
||||
default CONFIG_DCACHE_RAM_BASE = 0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
|
||||
default CONFIG_USE_INIT = 0
|
||||
default CONFIG_AP_CODE_IN_CAR = 0
|
||||
default CONFIG_MEM_TRAIN_SEQ = 2
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
|
||||
# default CONFIG_ENABLE_APIC_EXT_ID = 0
|
||||
# default CONFIG_APIC_ID_OFFSET = 0x10
|
||||
# default CONFIG_LIFT_BSP_APIC_ID = 0
|
||||
# default CONFIG_PCI_64BIT_PREF_MEM = 1
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E"
|
||||
default CONFIG_MAINBOARD_VENDOR = "ASUS"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
# Only use the option table in a normal image.
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_GDB_STUB = 0
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
|
||||
default CONFIG_ID_SECTION_OFFSET = 0x80
|
||||
|
||||
end
|
||||
|
|
@ -1,190 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
arch i386 end
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "mv dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
mainboardinit southbridge/via/k8t890/romstrap.inc
|
||||
ldscript /southbridge/via/k8t890/romstrap.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_939 # CPU
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
chip northbridge/amd/amdk8 # mc0
|
||||
device pci 18.0 on # Northbridge
|
||||
# Devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/via/vt8237r # Southbridge
|
||||
register "ide0_enable" = "1" # Enable IDE channel 0
|
||||
register "ide1_enable" = "1" # Enable IDE channel 1
|
||||
register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
|
||||
register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
|
||||
register "fn_ctrl_lo" = "0" # Enable SB functions
|
||||
register "fn_ctrl_hi" = "0xad" # Enable SB functions
|
||||
device pci 0.0 on end # HT
|
||||
device pci f.1 on end # IDE
|
||||
device pci 11.0 on # LPC
|
||||
chip drivers/generic/generic # DIMM 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip superio/winbond/w83627ehg # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2 (N/A on this board)
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 off # PS/2 keyboard (off)
|
||||
end
|
||||
device pnp 2e.106 off # Serial flash
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.007 off # GPIO 1
|
||||
end
|
||||
device pnp 2e.107 on # Game port
|
||||
io 0x60 = 0x201
|
||||
end
|
||||
device pnp 2e.207 on # MIDI
|
||||
io 0x62 = 0x330
|
||||
irq 0x70 = 0xa
|
||||
end
|
||||
device pnp 2e.307 off # GPIO 6
|
||||
end
|
||||
device pnp 2e.8 off # WDTO_PLED
|
||||
end
|
||||
device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup
|
||||
end
|
||||
device pnp 2e.109 off # GPIO 3
|
||||
end
|
||||
device pnp 2e.209 off # GPIO 4
|
||||
end
|
||||
device pnp 2e.309 on # GPIO5
|
||||
end
|
||||
device pnp 2e.a off # ACPI
|
||||
end
|
||||
device pnp 2e.b on # Hardware monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 0
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.0 off end # VIA LAN (off, other chip used)
|
||||
end
|
||||
chip southbridge/via/k8t890 # "Southbridge" K8T890
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License v2 as published by
|
||||
## the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
# uses CONFIG_USE_OPTION_TABLE
|
||||
# uses CONFIG_RAMTOP
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
# bx_b005+
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
default CONFIG_ROM_SIZE = 512 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 0
|
||||
default CONFIG_GENERATE_MP_TABLE = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME
|
||||
# Move the default coreboot CMOS range off of AMD RTC registers.
|
||||
default CONFIG_LB_CKS_RANGE_START = 49
|
||||
default CONFIG_LB_CKS_RANGE_END = 122
|
||||
default CONFIG_LB_CKS_LOC = 123
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_MAX_CPUS = 2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS = 1
|
||||
default CONFIG_LOGICAL_CPUS = 1
|
||||
default CONFIG_GENERATE_ACPI_TABLES = 1
|
||||
|
||||
# 1G memory hole
|
||||
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
|
||||
|
||||
# Opteron K8 1G HT support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
|
||||
|
||||
# HT Unit ID offset, default is 1, the typical one.
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
|
||||
|
||||
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
|
||||
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
|
||||
|
||||
# Make the SB HT chain on bus 0, default is not (0).
|
||||
# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
|
||||
|
||||
# bx_b005+ make the SB HT chain on bus 0.
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
|
||||
|
||||
# Only offset for SB chain?, default is yes(1).
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
|
||||
|
||||
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
|
||||
default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA.
|
||||
default CONFIG_USE_DCACHE_RAM = 1
|
||||
default CONFIG_DCACHE_RAM_BASE = 0xcc000
|
||||
default CONFIG_DCACHE_RAM_SIZE = 0x4000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
|
||||
default CONFIG_USE_INIT = 0
|
||||
default CONFIG_ENABLE_APIC_EXT_ID = 0
|
||||
default CONFIG_APIC_ID_OFFSET = 0x10
|
||||
default CONFIG_LIFT_BSP_APIC_ID = 0
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_MAINBOARD_VENDOR = "ASUS"
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
|
||||
# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 256 * 1024
|
||||
# More 1M for pgtbl.
|
||||
# default CONFIG_RAMTOP = 2048*1024
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_GDB_STUB = 0
|
||||
default CONFIG_USE_PRINTK_IN_CAR = 1
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
|
||||
end
|
||||
|
|
@ -1,167 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
|
||||
## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "mv dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
mainboardinit southbridge/via/k8t890/romstrap.inc
|
||||
ldscript /southbridge/via/k8t890/romstrap.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex # Root complex
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/amd/socket_AM2 # CPU
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
chip northbridge/amd/amdk8 # mc0
|
||||
device pci 18.0 on # Northbridge
|
||||
# Devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/via/vt8237r # Southbridge
|
||||
register "ide0_enable" = "1" # Enable IDE channel 0
|
||||
register "ide1_enable" = "1" # Enable IDE channel 1
|
||||
register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
|
||||
register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
|
||||
register "fn_ctrl_lo" = "0xc0" # Enable SB functions
|
||||
register "fn_ctrl_hi" = "0x1d" # Enable SB functions
|
||||
device pci 0.0 on end # HT
|
||||
device pci f.1 on end # IDE
|
||||
device pci 11.0 on # LPC
|
||||
chip drivers/generic/generic # DIMM 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic # DIMM 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip superio/ite/it8712f # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Environment controller
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x230
|
||||
irq 0x70 = 0x00
|
||||
end
|
||||
device pnp 2e.5 off end # PS/2 keyboard
|
||||
device pnp 2e.6 off end # PS/2 mouse
|
||||
device pnp 2e.7 off end # GPIO config
|
||||
device pnp 2e.8 off end # Midi port
|
||||
device pnp 2e.9 off end # Game port
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end
|
||||
device pci 12.0 on end # VIA LAN
|
||||
device pci 13.0 on end # br
|
||||
device pci 13.1 on end # br2 need to have it here to discover it
|
||||
end
|
||||
chip southbridge/via/k8t890 # "Southbridge" K8M890
|
||||
end
|
||||
end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License v2 as published by
|
||||
## the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_RAMTOP
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_MAINBOARD_RESOURCES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_HAVE_LOW_TABLES
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_VGA
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
# bx_b005+
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 0
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME
|
||||
# Move the default coreboot CMOS range off of AMD RTC registers.
|
||||
default CONFIG_LB_CKS_RANGE_START = 49
|
||||
default CONFIG_LB_CKS_RANGE_END = 122
|
||||
default CONFIG_LB_CKS_LOC = 123
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_MAX_CPUS = 2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS = 1
|
||||
default CONFIG_LOGICAL_CPUS = 1
|
||||
default CONFIG_GENERATE_ACPI_TABLES = 1
|
||||
default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
|
||||
default CONFIG_HAVE_LOW_TABLES = 0
|
||||
default CONFIG_HAVE_ACPI_RESUME = 1
|
||||
|
||||
# 1G memory hole
|
||||
# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
|
||||
|
||||
# Opteron K8 1G HT support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
|
||||
|
||||
# HT Unit ID offset, default is 1, the typical one.
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
|
||||
|
||||
# Real SB Unit ID, default is 0x20, mean don't touch it at last.
|
||||
# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
|
||||
|
||||
# Make the SB HT chain on bus 0, default is not (0).
|
||||
# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
|
||||
|
||||
# bx_b005+ make the SB HT chain on bus 0.
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
|
||||
|
||||
# Only offset for SB chain?, default is yes(1).
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
|
||||
|
||||
default CONFIG_VGA = 1
|
||||
default CONFIG_CONSOLE_VGA = 1 # Needed for VGA.
|
||||
default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA.
|
||||
default CONFIG_USE_DCACHE_RAM = 1
|
||||
default CONFIG_DCACHE_RAM_BASE = 0xcc000
|
||||
default CONFIG_DCACHE_RAM_SIZE = 0x4000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
|
||||
default CONFIG_USE_INIT = 0
|
||||
default CONFIG_ENABLE_APIC_EXT_ID = 0
|
||||
default CONFIG_APIC_ID_OFFSET = 0x10
|
||||
default CONFIG_LIFT_BSP_APIC_ID = 0
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_MAINBOARD_VENDOR = "ASUS"
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
|
||||
# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 256 * 1024
|
||||
# More 1M for pgtbl.
|
||||
default CONFIG_RAMTOP = 32768*1024
|
||||
# to 1MB
|
||||
default CONFIG_RAMBASE = 0x1F00000
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_GDB_STUB = 0
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
end
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
# Note: The -mcpu=p2 is important, or else... 'too few registers'.
|
||||
action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
# Note: The -mcpu=p2 is important, or else... 'too few registers'.
|
||||
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
# TODO: On-board graphics.
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
|
||||
device pci 1.0 on end # Chipset Graphics Controller (CGC)
|
||||
chip southbridge/intel/i82801xx # Southbridge
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # ISA bridge
|
||||
chip superio/smsc/smscsuperio # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 4
|
||||
end
|
||||
device pnp 2e.4 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 2e.9 on # Game port
|
||||
io 0x60 = 0x201
|
||||
end
|
||||
device pnp 2e.a on # Power-management events (PME)
|
||||
io 0x60 = 0x600
|
||||
end
|
||||
device pnp 2e.b on # MIDI port (MPU-401)
|
||||
io 0x60 = 0x330
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
device pci 1f.2 on end # USB
|
||||
device pci 1f.3 on end # SMbus
|
||||
device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip)
|
||||
device pci 1f.6 off end # AC'97 modem (N/A)
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb.
|
||||
|
||||
end
|
||||
|
|
@ -1,147 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i82810
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on # Onboard Video
|
||||
# device pci 1.0 on end
|
||||
end
|
||||
chip southbridge/intel/i82801xx # Southbridge
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
|
||||
device pci 1e.0 on # PCI Bridge
|
||||
# device pci 1.0 on end
|
||||
end
|
||||
device pci 1f.0 on # ISA/LPC? Bridge
|
||||
chip superio/smsc/lpc47b272
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.3 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Keyboard interrupt
|
||||
irq 0x72 = 12 # Mouse interrupt
|
||||
end
|
||||
device pnp 2e.a off end # ACPI
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
device pci 1f.2 on end # USB
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end # AC'97, no header on MEW-VM
|
||||
device pci 1f.6 off end # AC'97 Modem (MC'97)
|
||||
end
|
||||
end
|
||||
chip cpu/intel/socket_PGA370
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 512*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 11
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
|
||||
end
|
||||
|
|
@ -1,134 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 1 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 4.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.9 on # GPIO 3
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 4.1 on end # IDE
|
||||
device pci 4.2 on end # USB
|
||||
device pci 4.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "1"
|
||||
register "ide0_drive1_udma33_enable" = "1"
|
||||
register "ide1_drive0_udma33_enable" = "1"
|
||||
register "ide1_drive1_udma33_enable" = "1"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_MAX_CPUS = 2
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
end
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 1 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 4.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.9 on # GPIO 3
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 4.1 on end # IDE
|
||||
device pci 4.2 on end # USB
|
||||
device pci 4.3 on end # ACPI
|
||||
device pci 6.0 on end # Onboard SCSI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "1"
|
||||
register "ide0_drive1_udma33_enable" = "1"
|
||||
register "ide1_drive0_udma33_enable" = "1"
|
||||
register "ide1_drive1_udma33_enable" = "1"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_MAX_CPUS = 2
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 4.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # Consumer IR
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 4.1 on end # IDE
|
||||
device pci 4.2 on end # USB
|
||||
device pci 4.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 4.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.9 on # GPIO 3
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 4.1 on end # IDE
|
||||
device pci 4.2 on end # USB
|
||||
device pci 4.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
# TODO
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 4.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # Consumer IR
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 4.1 on end # IDE
|
||||
device pci 4.2 on end # USB
|
||||
device pci 4.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc97317 # Super I/O
|
||||
device pnp 2e.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC, advanced power control (APC)
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # Floppy (N/A on this board)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 off # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 off end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
# register "ide0_enable" = "1"
|
||||
# register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/model_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_SPLASH_GRAPHIC
|
||||
uses CONFIG_GX1_VIDEO
|
||||
uses CONFIG_GX1_VIDEOMODE
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
|
||||
## We want to support up to 1024x768@16 so we need 2MiB video memory.
|
||||
## Note: Higher resolutions might need faster SDRAM speed.
|
||||
default CONFIG_GX1_VIDEO = 1
|
||||
default CONFIG_GX1_VIDEOMODE = 0
|
||||
default CONFIG_SPLASH_GRAPHIC = 1
|
||||
default CONFIG_VIDEO_MB = 2
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_MAINBOARD_VENDOR = "AXUS"
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "TC320"
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
|
||||
|
||||
end
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 7.0 on # ISA bridge
|
||||
chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # Consumer IR
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
end
|
||||
device pnp 3f0.a on # ACPI
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 7.1 on end # IDE
|
||||
device pci 7.2 on end # USB
|
||||
device pci 7.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,129 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 on end # Ethernet (onboard)
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc97317 # Super I/O
|
||||
device pnp 2e.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC, Advanced power control (APC)
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # Floppy (N/A on this board)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 on # COM2 (used for smartcard reader)
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power management
|
||||
io 0x60 = 0xe8
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "0" # Not available/needed on this board
|
||||
end
|
||||
end
|
||||
chip cpu/amd/model_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
|
@ -1,103 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_SPLASH_GRAPHIC
|
||||
uses CONFIG_GX1_VIDEO
|
||||
uses CONFIG_GX1_VIDEOMODE
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## Enable VGA with a splash screen (only 640x480 to run on most monitors).
|
||||
## We want to support up to 1024x768@16 so we need 2MiB video memory.
|
||||
## Note: Higher resolutions might need faster SDRAM speed.
|
||||
default CONFIG_GX1_VIDEO = 1
|
||||
default CONFIG_GX1_VIDEOMODE = 0
|
||||
default CONFIG_SPLASH_GRAPHIC = 1
|
||||
default CONFIG_VIDEO_MB = 2
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_MAINBOARD_VENDOR = "BCOM"
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100"
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 2 # Soldered NIC, internal USB, no real slots
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc "
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
|
||||
|
||||
end
|
||||
|
|
@ -1,138 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 VIA Technologies, Inc.
|
||||
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object fadt.o
|
||||
object dsdt.o
|
||||
object acpi_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/via/cn700 # Northbridge
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # AGP Bridge
|
||||
device pci 0.1 on end # Error Reporting
|
||||
device pci 0.2 on end # Host Bus Control
|
||||
device pci 0.3 on end # Memory Controller
|
||||
device pci 0.4 on end # Power Management
|
||||
device pci 0.7 on end # V-Link Controller
|
||||
device pci 1.0 on end # PCI Bridge
|
||||
chip southbridge/via/vt8237r # Southbridge
|
||||
# Enable both IDE channels.
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
# Both cables are 40pin.
|
||||
register "ide0_80pin_cable" = "0"
|
||||
register "ide1_80pin_cable" = "0"
|
||||
register "fn_ctrl_lo" = "0x80"
|
||||
register "fn_ctrl_hi" = "0x1d"
|
||||
device pci f.0 on end # IDE
|
||||
device pci 10.0 on end # UHCI
|
||||
device pci 10.1 on end # UHCI
|
||||
device pci 10.2 on end # UHCI
|
||||
device pci 10.3 on end # UHCI
|
||||
device pci 10.4 on end # EHCI
|
||||
device pci 11.0 on # Southbridge LPC
|
||||
chip superio/winbond/w83697hf # Super I/O
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 off end # Consumer IR
|
||||
device pnp 2e.7 off end # Game port, GPIO 1
|
||||
device pnp 2e.8 off end # MIDI port, GPIO 5
|
||||
device pnp 2e.9 off end # GPIO 2-4
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HWM
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 11.5 on end # AC'97 audio
|
||||
device pci 12.0 on end # Ethernet
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/via/model_c7 # VIA C7
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2008 VIA Technologies, Inc.
|
||||
## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_IOAPIC
|
||||
|
||||
default CONFIG_ROM_SIZE = 512 * 1024
|
||||
default CONFIG_SMP = 1
|
||||
default CONFIG_IOAPIC = 1
|
||||
default CONFIG_VIDEO_MB = 32
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_PCI_ROM_RUN = 0
|
||||
default CONFIG_CONSOLE_VGA = 0
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 10
|
||||
default CONFIG_GENERATE_ACPI_TABLES = 0
|
||||
default CONFIG_HAVE_OPTION_TABLE = 1
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_USE_FALLBACK_IMAGE = 1
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
|
||||
default HOSTCC = "gcc"
|
||||
|
||||
end
|
||||
|
|
@ -1,126 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 7.0 on # ISA bridge
|
||||
chip superio/smsc/smscsuperio # Super I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.4 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.5 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.7 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.8 on # Aux I/O
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 7.1 on end # IDE
|
||||
device pci 7.2 on end # USB
|
||||
device pci 7.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,235 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
#dir /drivers/si/3114
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object get_bus_conf.o
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
# sample config for broadcom/blast
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0
|
||||
chip southbridge/broadcom/bcm5780 # HT2000
|
||||
device pci 0.0 on end # PXB 1 0x0130
|
||||
device pci 1.0 on # PXB 2 0x0130
|
||||
device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
|
||||
device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
|
||||
end
|
||||
device pci 2.0 on end # PCI E 1 #0x0132
|
||||
device pci 3.0 on end # PCI E 2
|
||||
device pci 4.0 on end # PCI E 3
|
||||
device pci 5.0 on end # PCI E 4
|
||||
end
|
||||
chip southbridge/broadcom/bcm5785 # HT1000
|
||||
device pci 0.0 on # HT PXB 0x0036
|
||||
device pci d.0 on end # PPBX 0x0104
|
||||
device pci e.0 on end # SATA 0x024a
|
||||
end
|
||||
device pci 1.0 on # Legacy pci main 0x0205
|
||||
chip drivers/i2c/i2cmux2 # pca9554 smbus mux
|
||||
device i2c 71 on end #0 pca9554 0
|
||||
device i2c 71 on end #0 pca9554 1
|
||||
device i2c 71 on end #0 pca9554 2
|
||||
device i2c 71 on end #0 pca9554 3
|
||||
device i2c 71 on end #0 pca9554 4
|
||||
device i2c 71 on end #0 pca9554 5
|
||||
device i2c 71 on #0 pca9554 6
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 71 on #1 pca9554 7
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
device pci 1.1 on end # IDE 0x0214
|
||||
device pci 1.2 on # LPC 0x0234
|
||||
chip superio/nsc/pc87417
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # Mouse
|
||||
device pnp 2e.6 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.f off end # XBUS
|
||||
device pnp 2e.10 on #RTC
|
||||
io 0x60 = 0x70
|
||||
io 0x62 = 0x72
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1.3 on end # WDTimer 0x0238
|
||||
device pci 1.4 on end # XIOAPIC0 0x0235
|
||||
device pci 1.5 on end # XIOAPIC1
|
||||
device pci 1.6 on end # XIOAPIC2
|
||||
device pci 2.0 on end # USB 0x0223
|
||||
device pci 2.1 on end # USB
|
||||
device pci 2.2 on end # USB
|
||||
device pci 4.0 on end # it is in bcm5785_0 bus
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
|
||||
|
||||
end #pci_domain
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 off end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,260 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=4
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#1G memory hole
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
|
||||
#VGA Console
|
||||
#default CONFIG_CONSOLE_VGA=1
|
||||
#default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#HT Unit ID offset
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0x6
|
||||
|
||||
#real SB Unit ID
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
|
||||
|
||||
#make the SB HT chain on bus 0
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xcf000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x1000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="blast"
|
||||
default CONFIG_MAINBOARD_VENDOR="Broadcom"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
|
||||
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
device pci a.0 on end # NIC (onboard)
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 14.0 on # ISA bridge
|
||||
# chip superio/nsc/pc97307 # Super I/O
|
||||
chip superio/nsc/pc97317 # Super I/O (FIXME: Should be PC97307!)
|
||||
device pnp 15c.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 15c.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 15c.2 on # RTC, APC
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 15c.3 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 15c.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 15c.5 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 15c.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 15c.7 on # GPIO 1
|
||||
end
|
||||
device pnp 15c.8 on # Power management
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 14.1 on end # IDE
|
||||
device pci 14.2 on end # USB
|
||||
device pci 14.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 5 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
if CONFIG_HAVE_HARD_RESET object reset.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/x86/sse_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/sse_disable.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/e7520 # mch
|
||||
device pci_domain 0 on
|
||||
chip southbridge/intel/i82801er # i82801er
|
||||
# USB ports
|
||||
device pci 1d.0 on end
|
||||
device pci 1d.1 on end
|
||||
device pci 1d.2 on end
|
||||
device pci 1d.3 on end
|
||||
device pci 1d.7 on end
|
||||
|
||||
# -> Bridge
|
||||
device pci 1e.0 on end
|
||||
|
||||
# -> ISA
|
||||
device pci 1f.0 on
|
||||
chip superio/nsc/pc8374
|
||||
device pnp 2e.0 off end
|
||||
device pnp 2e.1 off end
|
||||
device pnp 2e.2 off end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end
|
||||
device pnp 2e.5 off end
|
||||
device pnp 2e.6 off end
|
||||
device pnp 2e.7 off end
|
||||
device pnp 2e.8 off end
|
||||
end
|
||||
end
|
||||
# -> IDE
|
||||
device pci 1f.1 on end
|
||||
# -> SATA
|
||||
device pci 1f.2 on end
|
||||
device pci 1f.3 on end
|
||||
|
||||
register "pirq_a_d" = "0x8e8b8f80"
|
||||
register "pirq_e_h" = "0x80808080"
|
||||
end
|
||||
device pci 00.0 on end
|
||||
device pci 00.1 on end
|
||||
device pci 01.0 on end
|
||||
device pci 02.0 on
|
||||
chip southbridge/intel/pxhd # pxhd1
|
||||
# Bus bridges and ioapics usually bus 1
|
||||
device pci 0.0 on
|
||||
# On board gig e1000
|
||||
chip drivers/generic/generic
|
||||
device pci 03.0 on end
|
||||
device pci 03.1 on end
|
||||
end
|
||||
end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 0.3 on end
|
||||
end
|
||||
end
|
||||
device pci 04.0 on end
|
||||
device pci 06.0 on end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA604 # cpu 0
|
||||
device apic 0 on end
|
||||
end
|
||||
chip cpu/intel/socket_mPGA604 # cpu 1
|
||||
device apic 6 on end
|
||||
end
|
||||
end
|
||||
register "intrline" = "0x00070100"
|
||||
end
|
||||
|
||||
|
|
@ -1,228 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_BTEXT
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CONFIG_OBJCOPY
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=1048576
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Delay timer options
|
||||
## Use timer2
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=9
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=4
|
||||
default CONFIG_LOGICAL_CPUS=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
|
||||
default CONFIG_MAINBOARD_VENDOR= "Supermicro"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
|
||||
###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (coreboot plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD=1
|
||||
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
#default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
##
|
||||
## Don't enable the btext console
|
||||
##
|
||||
default CONFIG_CONSOLE_BTEXT=0
|
||||
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/x86/sse_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/sse_disable.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
## This does not look right but it is a literal conversion of the
|
||||
## old version of this file.
|
||||
chip northbridge/intel/i855pm
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
device pci 1.0 on end
|
||||
chip southbridge/intel/i82801dbm
|
||||
# pci 11.0 on end
|
||||
# pci 11.1 on end
|
||||
# pci 11.2 on end
|
||||
# pci 11.3 on end
|
||||
# pci 11.4 on end
|
||||
# pci 11.5 on end
|
||||
# pci 11.6 on end
|
||||
# pci 12.0 on end
|
||||
register "enable_usb" = "0"
|
||||
register "enable_native_ide" = "0"
|
||||
register "enable_usb" = "0"
|
||||
register "enable_native_ide" = "0"
|
||||
chip superio/winbond/w83627hf # link 1
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GAME_MIDI_GIPO1
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
register "com1" = "{1}"
|
||||
# register "com1" = "{1, 0, 0x3f8, 4}"
|
||||
# register "lpt" = "{1}"
|
||||
end
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
chip cpu/intel/socket_mPGA479M
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_UDELAY_IO
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 1024*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## use io based udelay function
|
||||
##
|
||||
default CONFIG_UDELAY_IO=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=5
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
end
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
default CONFIG_ROM_SIZE = 512 * 1024
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 32 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
|
||||
# VGA console
|
||||
if CONFIG_CONSOLE_VGA
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
end
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
dir /devices
|
||||
config chip.h
|
||||
|
||||
chip cpu/amd/sc520
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
device pci 12.0 on end # enet
|
||||
device pci 14.0 on end # 69000
|
||||
# register "com1" = "{1}"
|
||||
# register "com1" = "{1, 0, 0x3f8, 4}"
|
||||
end
|
||||
|
||||
end
|
||||
|
|
@ -1,121 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
|
||||
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
|
||||
# VGA support
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
#uses CONFIG_LEGACY_VGABIOS
|
||||
#uses VGABIOS_START
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=2
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
end
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
|
||||
#compile cache_as_ram.c to auto.inc
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
|
||||
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
|
||||
# How to get these? Boot linux and do this:
|
||||
# rdmsr 0x51400025
|
||||
register "lpc_serirq_enable" = "0x0000105a"
|
||||
# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
|
||||
register "lpc_serirq_polarity" = "0x0000EFA5"
|
||||
# mode is high 10 bits (determined from code)
|
||||
register "lpc_serirq_mode" = "1"
|
||||
# Don't yet know how to find this.
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "0" #0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci f.0 on # ISA Bridge
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci f.1 on end # Flash controller
|
||||
device pci f.2 on end # IDE controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,180 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
default CONFIG_CONSOLE_VGA=0
|
||||
default CONFIG_VIDEO_MB=8
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=9
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 32768
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx1
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
device pci 12.0 on
|
||||
chip superio/nsc/pc97317
|
||||
device pnp 2e.0 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # FDC
|
||||
end
|
||||
device pnp 2e.4 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power Management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
register "com1" = "{115200}"
|
||||
register "com2" = "{38400}"
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 off end # Audio
|
||||
device pci 12.4 off end # VGA
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/model_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,164 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=2
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
default CONFIG_VIDEO_MB = 0
|
||||
|
||||
end
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
## we don't use CONFIG_USE_DCACHE_RAM by default
|
||||
default CONFIG_USE_DCACHE_RAM=0
|
||||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (coreboot plus bootloader) will live in the boot rom chip.
|
||||
##
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
|
||||
|
||||
##
|
||||
## Compute where this copy of coreboot will start in the boot rom
|
||||
##
|
||||
default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
|
||||
|
||||
##
|
||||
## Compute a range of ROM that can cached to speed up coreboot,
|
||||
## execution speed.
|
||||
##
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
|
||||
##
|
||||
default CONFIG_XIP_ROM_SIZE=32*1024
|
||||
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
|
||||
## ALL dependencies for CONFIG_USE_DCACHE_RAM go here.
|
||||
## That way, later, we can simply yank them if we wish.
|
||||
## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case.
|
||||
## we do not use failover yet in this case. This is a work in progress.
|
||||
if CONFIG_USE_DCACHE_RAM
|
||||
##
|
||||
##
|
||||
mainboardinit arch/i386/init/entry.S
|
||||
mainboardinit arch/i386/init/car.S
|
||||
ldscript /arch/i386/init/ldscript.ld
|
||||
|
||||
## The main code for the rom section is called rom.c
|
||||
initobject rom.o
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## end of CONFIG_USE_DCACHE_RAM bits.
|
||||
##
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip cpu/emulation/qemu-x86
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
|
||||
chip southbridge/intel/i82371eb # southbridge
|
||||
device pci 01.0 on end
|
||||
device pci 01.1 on end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
|
||||
# register "com1" = "{1}"
|
||||
# register "com1" = "{1, 0, 0x3f8, 4}"
|
||||
end
|
||||
end
|
||||
|
|
@ -1,140 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_WRITE_HIGH_TABLES
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
|
||||
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
|
||||
uses CONFIG_UDELAY_IO
|
||||
default CONFIG_UDELAY_IO=1
|
||||
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=6
|
||||
|
||||
default CONFIG_WRITE_HIGH_TABLES=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Option ROM init
|
||||
##
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## known-good settings for qemu
|
||||
default CONFIG_DCACHE_RAM_BASE=0x8f000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x1000
|
||||
|
||||
|
||||
|
||||
|
||||
end
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i440bx # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # PCI/AGP bridge
|
||||
chip southbridge/intel/i82371eb # Southbridge
|
||||
device pci 7.0 on # ISA bridge
|
||||
chip superio/ite/it8671f # Super I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.2 on # COM2 / IR
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.3 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.4 on # APC
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 3f0.6 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 7.1 on end # IDE
|
||||
device pci 7.2 on end # USB
|
||||
device pci 7.3 on end # ACPI
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "ide_legacy_enable" = "1"
|
||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
||||
register "ide0_drive0_udma33_enable" = "0"
|
||||
register "ide0_drive1_udma33_enable" = "0"
|
||||
register "ide1_drive0_udma33_enable" = "0"
|
||||
register "ide1_drive1_udma33_enable" = "0"
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
|
||||
end
|
||||
|
|
@ -1,270 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
|
||||
## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/failovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
else
|
||||
if CONFIG_AP_CODE_IN_CAR
|
||||
makerule ./apc_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
|
||||
end
|
||||
ldscript /arch/i386/init/ldscript_apc.lb
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit southbridge/sis/sis966/romstrap.inc
|
||||
ldscript /southbridge/sis/sis966/romstrap.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/sis/sis966/romstrap.inc
|
||||
ldscript /southbridge/sis/sis966/romstrap.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/sis/sis966
|
||||
device pci 0.0 on end # Northbridge
|
||||
device pci 1.0 on # AGP bridge
|
||||
device pci 0.0 on end
|
||||
end
|
||||
device pci 2.0 on # LPC
|
||||
chip superio/ite/it8716f
|
||||
device pnp 2e.0 off # Floppy (N/A)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2 (N/A)
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 off # Parallel port (N/A)
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # EC
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x230
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 off # PS/2 keyboard (N/A)
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 off # Mouse (N/A)
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.8 off # MIDI (N/A)
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 10
|
||||
end
|
||||
device pnp 2e.9 off # GAME (N/A)
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR (N/A)
|
||||
end
|
||||
end
|
||||
|
||||
device pci 2.5 off end # IDE (SiS5513)
|
||||
device pci 2.6 off end # Modem (SiS7013)
|
||||
device pci 2.7 off end # Audio (SiS7012)
|
||||
device pci 3.0 on end # USB (SiS7001,USB1.1)
|
||||
device pci 3.1 on end # USB (SiS7001,USB1.1)
|
||||
device pci 3.3 on end # USB (SiS7002,USB2.0)
|
||||
device pci 4.0 on end # NIC (SiS191)
|
||||
device pci 5.0 on end # SATA (SiS1183,Native Mode)
|
||||
device pci 6.0 on end # PCI-e x1
|
||||
device pci 7.0 on end # PCI-e x1
|
||||
device pci a.0 off end
|
||||
device pci b.0 off end
|
||||
device pci c.0 off end
|
||||
device pci d.0 off end
|
||||
device pci e.0 off end
|
||||
device pci f.0 off end # HD Audio (SiS7502)
|
||||
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 off end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 off end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
end #root_complex
|
||||
|
|
@ -1,354 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
|
||||
## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_USBDEBUG_DIRECT
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
#default CONFIG_ROM_SIZE=0x100000
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
||||
#FALLBACK: 256K-4K
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
#FAILOVER: 4K
|
||||
default CONFIG_FAILOVER_SIZE=0x01000
|
||||
|
||||
#more 1M for pgtbl
|
||||
default CONFIG_RAMTOP=2048*1024
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=0
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=1
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#default CONFIG_SERIAL_CPU_INIT=0
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=0
|
||||
default CONFIG_APIC_ID_OFFSET=0x10
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#Opteron K8 1G HT Support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#default CONFIG_USBDEBUG_DIRECT=0
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
default CONFIG_AP_CODE_IN_CAR=0
|
||||
default CONFIG_MEM_TRAIN_SEQ=2
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
|
||||
default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,362 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/failovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./cache_as_ram_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
else
|
||||
if CONFIG_AP_CODE_IN_CAR
|
||||
makerule ./apc_auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
|
||||
end
|
||||
ldscript /arch/i386/init/ldscript_apc.lb
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## ROMSTRAP table for MCP55
|
||||
##
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
|
||||
ldscript /southbridge/nvidia/mcp55/romstrap.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
|
||||
ldscript /southbridge/nvidia/mcp55/romstrap.lds
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_HAVE_FAILOVER_BOOT
|
||||
if CONFIG_USE_FAILOVER_IMAGE
|
||||
ldscript /arch/i386/lib/failover_failover.lds
|
||||
end
|
||||
else
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
end
|
||||
|
||||
if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
|
||||
object fanctl.o
|
||||
end
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject cache_as_ram_auto.o
|
||||
else
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## ACPI Support
|
||||
##
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object acpi_tables.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "mv $(CURDIR)/dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_AM2
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 #mc0
|
||||
device pci 18.0 on # devices on link 0, link 0 == LDT 0
|
||||
chip southbridge/nvidia/mcp55
|
||||
device pci 0.0 on end # HT
|
||||
device pci 1.0 on # LPC
|
||||
chip superio/ite/it8716f
|
||||
# Floppy and any LDN
|
||||
device pnp 2e.0 on
|
||||
# Watchdog from CLKIN, CLKIN = 24 MHz
|
||||
irq 0x23 = 0x11
|
||||
# Serial Flash (SPI only)
|
||||
#0x24 = 0x1a
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.4 on # EC
|
||||
io 0x60 = 0x290
|
||||
io 0x62 = 0x230
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO, SPI flash
|
||||
# pin 84 is not GP10
|
||||
irq 0x25 = 0x0
|
||||
# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
|
||||
irq 0x26 = 0x43
|
||||
# pin 13 is GP35
|
||||
irq 0x27 = 0x20
|
||||
# pin 70 is not GP46
|
||||
#irq 0x28 = 0x0
|
||||
# pin 6,3,128,127,126 is GP63,64,65,66,67
|
||||
irq 0x29 = 0x81
|
||||
# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
|
||||
#irq 0x2c = 0x1f
|
||||
# Simple I/O base
|
||||
io 0x62 = 0x800
|
||||
# Serial Flash I/O (SPI only)
|
||||
io 0x64 = 0x820
|
||||
# watch dog force timeout (parallel flash only)
|
||||
#irq 0x71 = 0x1
|
||||
# No WDT interrupt
|
||||
irq 0x72 = 0x0
|
||||
# GPIO pin set 1 disable internal pullup
|
||||
irq 0xb8 = 0x0
|
||||
# GPIO pin set 5 enable internal pullup
|
||||
irq 0xbc = 0x01
|
||||
# SIO pin set 1 alternate function
|
||||
#irq 0xc0 = 0x0
|
||||
# SIO pin set 2 mixed function
|
||||
irq 0xc1 = 0x43
|
||||
# SIO pin set 3 mixed function
|
||||
irq 0xc2 = 0x20
|
||||
# SIO pin set 4 alternate function
|
||||
#irq 0xc3 = 0x0
|
||||
# SIO pin set 1 input mode
|
||||
#irq 0xc8 = 0x0
|
||||
# SIO pin set 2 input mode
|
||||
irq 0xc9 = 0x0
|
||||
# SIO pin set 4 input mode
|
||||
#irq 0xcb = 0x0
|
||||
# Generate SMI# on EC IRQ
|
||||
#irq 0xf0 = 0x10
|
||||
# SMI# level trigger
|
||||
#irq 0xf1 = 0x40
|
||||
# HWMON alert beep pin location
|
||||
irq 0xf6 = 0x28
|
||||
end
|
||||
device pnp 2e.8 off # MIDI
|
||||
io 0x60 = 0x300
|
||||
irq 0x70 = 10
|
||||
end
|
||||
device pnp 2e.9 off # GAME
|
||||
io 0x60 = 0x220
|
||||
end
|
||||
device pnp 2e.a off end # CIR
|
||||
end
|
||||
end
|
||||
device pci 1.1 on # SM 0
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
#WTF?!? We already have device pci 1.1 in the section above
|
||||
device pci 1.1 on # SM 1
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AZA
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # NIC
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end #device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
end #root_complex
|
||||
|
|
@ -1,364 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 AMD
|
||||
## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_USE_FAILOVER_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_FAILOVER_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_FAILOVER_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_USBDEBUG_DIRECT
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
|
||||
uses CONFIG_WRITE_HIGH_TABLES
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_AP_CODE_IN_CAR
|
||||
|
||||
uses CONFIG_MEM_TRAIN_SEQ
|
||||
|
||||
uses CONFIG_WAIT_BEFORE_CPUS_INIT
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
|
||||
|
||||
uses CONFIG_ID_SECTION_OFFSET
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
#default CONFIG_ROM_SIZE=0x100000
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
|
||||
#FALLBACK: 256K-4K
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
#FAILOVER: 4K
|
||||
default CONFIG_FAILOVER_SIZE=0x01000
|
||||
|
||||
#more 1M for pgtbl
|
||||
default CONFIG_RAMTOP=2048*1024
|
||||
|
||||
##
|
||||
## Set-up automatic fan control
|
||||
##
|
||||
default CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL=1
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
default CONFIG_HAVE_FAILOVER_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=11
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
## HIGH tables support
|
||||
default CONFIG_WRITE_HIGH_TABLES=1
|
||||
|
||||
## ACPI tables will be included
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=1
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
#default CONFIG_SERIAL_CPU_INIT=0
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=0
|
||||
default CONFIG_APIC_ID_OFFSET=0x10
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#Opteron K8 1G HT Support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
#default CONFIG_USBDEBUG_DIRECT=1
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x08000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
default CONFIG_AP_CODE_IN_CAR=0
|
||||
default CONFIG_MEM_TRAIN_SEQ=2
|
||||
default CONFIG_WAIT_BEFORE_CPUS_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="m57sli"
|
||||
default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
default CONFIG_ID_SECTION_OFFSET=0x80
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,210 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2006 AMD
|
||||
## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
|
||||
##
|
||||
## Copyright (C) 2007 University of Mannheim
|
||||
## Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
|
||||
##
|
||||
## Copyright (C) 2009 University of Heidelberg
|
||||
## Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
object get_bus_conf.o
|
||||
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
else
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
|
||||
# config for hp/dl145_g3
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8 # northbridge
|
||||
device pci 18.0 on # devices on link 0
|
||||
chip southbridge/broadcom/bcm21000 # HT2100
|
||||
device pci 0.0 on
|
||||
end # bridge to slot PCI-E 4x ??
|
||||
device pci 1.0 on
|
||||
end
|
||||
device pci 2.0 on
|
||||
end # unused
|
||||
device pci 3.0 on # bridge to slot PCI-E 16x ??
|
||||
end
|
||||
device pci 4.0 on
|
||||
end # unused
|
||||
device pci 5.0 on
|
||||
device pci 4.0 on end # BCM5715 NIC
|
||||
device pci 4.1 on end # BCM5715 NIC
|
||||
end
|
||||
end
|
||||
chip southbridge/broadcom/bcm5785 # HT1000
|
||||
device pci 0.0 on # HT PXB 0x0036
|
||||
device pci d.0 on end # PCI/PCI-X bridge 0x0104
|
||||
device pci e.0 on end # SATA 0x024a
|
||||
end
|
||||
device pci 1.0 on end # Legacy pci main 0x0205
|
||||
device pci 1.1 on end # IDE 0x0214
|
||||
device pci 1.2 on # LPC 0x0234
|
||||
chip superio/nsc/pc87417
|
||||
device pnp 4e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 4e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 4e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 4e.3 off # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.4 off end # SWC
|
||||
device pnp 4e.5 off end # Mouse
|
||||
device pnp 4e.6 off # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 4e.7 off end # GPIO
|
||||
device pnp 4e.f off end # XBUS
|
||||
device pnp 4e.10 on #RTC
|
||||
io 0x60 = 0x70
|
||||
io 0x62 = 0x72
|
||||
end
|
||||
end # end superio
|
||||
end # end pci 1.2
|
||||
device pci 1.3 off end # WDTimer 0x0238
|
||||
device pci 1.4 on end # XIOAPIC0 0x0235
|
||||
device pci 1.5 on end # XIOAPIC1
|
||||
device pci 1.6 on end # XIOAPIC2
|
||||
device pci 2.0 on end # USB 0x0223
|
||||
device pci 2.1 on end # USB
|
||||
device pci 2.2 on end # USB
|
||||
device pci 3.0 on end # VGA
|
||||
end
|
||||
end
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # amdk8
|
||||
|
||||
end #pci_domain
|
||||
end
|
||||
|
||||
|
||||
|
|
@ -1,328 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2006 AMD
|
||||
## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
|
||||
##
|
||||
## Copyright (C) 2007 University of Mannheim
|
||||
## Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for Uni Mannheim
|
||||
## Copyright (C) 2009 University of Heidelberg
|
||||
## Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_ACPI_SSDTX_NUM
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_HAVE_INIT_TIMER
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_HW_MEM_HOLE_SIZEK
|
||||
uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
|
||||
uses CONFIG_K8_HT_FREQ_1G_SUPPORT
|
||||
|
||||
uses CONFIG_HT_CHAIN_UNITID_BASE
|
||||
uses CONFIG_HT_CHAIN_END_UNITID_BASE
|
||||
uses CONFIG_SB_HT_CHAIN_ON_BUS0
|
||||
uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
|
||||
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
|
||||
uses CONFIG_SERIAL_CPU_INIT
|
||||
|
||||
uses CONFIG_ENABLE_APIC_EXT_ID
|
||||
uses CONFIG_APIC_ID_OFFSET
|
||||
uses CONFIG_LIFT_BSP_APIC_ID
|
||||
|
||||
uses CONFIG_PCI_64BIT_PREF_MEM
|
||||
|
||||
uses CONFIG_RAMTOP
|
||||
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
#more 1M for pgtbl
|
||||
default CONFIG_RAMTOP=2048*1024
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=15
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=4
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
|
||||
default CONFIG_SERIAL_CPU_INIT=0
|
||||
|
||||
default CONFIG_ENABLE_APIC_EXT_ID=0
|
||||
default CONFIG_APIC_ID_OFFSET=0x8
|
||||
default CONFIG_LIFT_BSP_APIC_ID=1
|
||||
|
||||
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
|
||||
#2G
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
#1G
|
||||
default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
|
||||
#512M
|
||||
#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
|
||||
|
||||
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
|
||||
#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
|
||||
|
||||
#Opteron K8 1G HT Support
|
||||
default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
|
||||
#HT Unit ID offset, default is 1, the typical one
|
||||
default CONFIG_HT_CHAIN_UNITID_BASE=0x06
|
||||
|
||||
#real SB Unit ID, default is 0x20, mean dont touch it at last
|
||||
default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
|
||||
|
||||
#make the SB HT chain on bus 0, default is not (0)
|
||||
default CONFIG_SB_HT_CHAIN_ON_BUS0=2
|
||||
|
||||
#only offset for SB chain?, default is yes(1)
|
||||
#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
|
||||
|
||||
#allow capable device use that above 4G
|
||||
#default CONFIG_PCI_64BIT_PREF_MEM=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xcc000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x04000
|
||||
default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="DL145 G3"
|
||||
default CONFIG_MAINBOARD_VENDOR="HP"
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
#enabel printk in CAR by default
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
makerule ./auto.E
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
|
||||
action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/x86/mmx_disable.inc
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
# TODO: i810E actually!
|
||||
chip northbridge/intel/i82810 # Northbridge
|
||||
device apic_cluster 0 on # APIC cluster
|
||||
chip cpu/intel/socket_PGA370 # CPU
|
||||
device apic 0 on end # APIC
|
||||
end
|
||||
end
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end # Host bridge
|
||||
device pci 1.0 on end # Onboard VGA
|
||||
chip southbridge/intel/i82801xx # Southbridge
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # ISA/LPC bridge
|
||||
# TODO: PC87364 actually!
|
||||
# TODO: Check Super I/O settings and compare to superiotool -d.
|
||||
chip superio/nsc/pc87360 # Super I/O
|
||||
device pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 3
|
||||
end
|
||||
device pnp 2e.2 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # PS/2 mouse
|
||||
device pnp 2e.6 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # ACB
|
||||
device pnp 2e.9 off end # FSCM
|
||||
device pnp 2e.a off end # WDT
|
||||
end
|
||||
end
|
||||
device pci 1f.1 on end # IDE
|
||||
device pci 1f.2 on end # USB
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 on end # AC'97 audio
|
||||
device pci 1f.6 off end # AC'97 modem (N/A ?)
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,101 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VGA_ROM_RUN
|
||||
uses CONFIG_WRITE_HIGH_TABLES
|
||||
uses CONFIG_VIDEO_MB
|
||||
|
||||
default CONFIG_ROM_SIZE = 512 * 1024
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 3
|
||||
default CONFIG_MAINBOARD_VENDOR = "HP"
|
||||
default CONFIG_MAINBOARD_PART_NUMBER = "e-Vectra P2706T"
|
||||
default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3 # 8n1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
|
||||
default CONFIG_UDELAY_TSC = 1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
|
||||
default CONFIG_CONSOLE_VGA = 1
|
||||
default CONFIG_PCI_ROM_RUN = 1
|
||||
default CONFIG_VGA_ROM_RUN = 1
|
||||
default CONFIG_WRITE_HIGH_TABLES = 1
|
||||
default CONFIG_VIDEO_MB = 1
|
||||
end
|
||||
|
|
@ -1,185 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on end # LDT 0
|
||||
device pci 18.0 on # LDT 1
|
||||
chip southbridge/amd/amd8131
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/nsc/pc87366
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # Mouse
|
||||
device pnp 2e.6 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # ACB
|
||||
device pnp 2e.9 off end # FSCM
|
||||
device pnp 2e.a off end # WDT
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on end
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # LDT2
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
chip cpu/amd/socket_940
|
||||
device apic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=12
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=1
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=1
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xcf000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x1000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="E325"
|
||||
default CONFIG_MAINBOARD_VENDOR="IBM"
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
end
|
||||
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/amd/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/amd/car/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
config chip.h
|
||||
|
||||
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/socket_940
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device pci_domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on end # LDT 0
|
||||
device pci 18.0 on # LDT 1
|
||||
chip southbridge/amd/amd8131
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
chip southbridge/amd/amd8111
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 on end
|
||||
device pci 1.0 off end
|
||||
device pci 5.0 on end # ATI Rage XL
|
||||
end
|
||||
device pci 1.0 on
|
||||
chip superio/nsc/pc87366
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 off # Com 2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Com 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # SWC
|
||||
device pnp 2e.5 off end # Mouse
|
||||
device pnp 2e.6 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
device pnp 2e.8 off end # ACB
|
||||
device pnp 2e.9 off end # FSCM
|
||||
device pnp 2e.a off end # WDT
|
||||
end
|
||||
end
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
device pci 1.3 on end
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
device pci 18.0 on end # LDT2
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,227 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=524288
|
||||
|
||||
##
|
||||
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
|
||||
##
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=12
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=2
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
#VGA
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_BASE=0xcf000
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x1000
|
||||
default CONFIG_USE_INIT=0
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="E326"
|
||||
default CONFIG_MAINBOARD_VENDOR="IBM"
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
|
||||
#default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00004000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,157 +0,0 @@
|
|||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (coreboot plus bootloader) will live in the boot rom chip.
|
||||
##
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
|
||||
##
|
||||
## Compute where this copy of coreboot will start in the boot rom
|
||||
##
|
||||
default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
|
||||
|
||||
##
|
||||
## Compute a range of ROM that can cached to speed up coreboot,
|
||||
## execution speed.
|
||||
##
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
|
||||
##
|
||||
default CONFIG_XIP_ROM_SIZE=65536
|
||||
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
#dir /pc80
|
||||
#config chip.h
|
||||
|
||||
chip northbridge/amd/gx1
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
|
||||
device pci 12.0 on
|
||||
chip superio/winbond/w83977f
|
||||
device pnp 3f0.0 on # FDC
|
||||
irq 0x70 = 6
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
register "com1" = "{115200}"
|
||||
device pnp 3f0.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
register "com2" = "{115200}"
|
||||
device pnp 3f0.4 on # RTC
|
||||
io 0x60 = 0x070
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 3f0.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Int 1 for PS/2 keyboard
|
||||
irq 0x72 = 12 # Int 12 for PS/2 mouse
|
||||
end
|
||||
device pnp 3f0.6 off # IR
|
||||
end
|
||||
device pnp 3f0.7 off # GPIO1
|
||||
end
|
||||
device pnp 3f0.8 off # GPIO
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA onboard
|
||||
|
||||
end
|
||||
|
||||
device pci 0e.0 on end # ETH0
|
||||
device pci 13.0 on end # USB
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/model_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,145 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_UDELAY_IO
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
default CONFIG_UDELAY_IO=1
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
# FIXME: There's an irq_tables.c file, but CONFIG_GENERATE_PIRQ_TABLE is 0.
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=0
|
||||
default CONFIG_IRQ_SLOT_COUNT=2
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 65536
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
default CONFIG_VIDEO_MB = 0
|
||||
|
||||
end
|
||||
|
|
@ -1,163 +0,0 @@
|
|||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
#dir /pc80
|
||||
#config chip.h
|
||||
|
||||
chip northbridge/amd/gx1
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
device pci 0a.0 on end # ETH0
|
||||
device pci 0b.0 off end # ETH1
|
||||
device pci 0c.0 on end # ETH2
|
||||
device pci 0f.0 on end # PCI slot
|
||||
device pci 12.0 on
|
||||
chip superio/winbond/w83977tf
|
||||
device pnp 2e.0 on # FDC
|
||||
irq 0x70 = 6
|
||||
end
|
||||
device pnp 2e.1 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
register "com1" = "{115200}"
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
register "com2" = "{115200}"
|
||||
device pnp 2e.4 off # Reserved
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
|
||||
irq 0x72 = 0x0c # Int 12 for PS/2 mouse
|
||||
end
|
||||
device pnp 2e.6 on # IR
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # GAME/MIDI/GPIO1
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
device pnp 2e.8 on # GPIO2
|
||||
io 0x60 = 0x110
|
||||
end
|
||||
device pnp 2e.9 on # GPIO3
|
||||
io 0x60 = 0x120
|
||||
end
|
||||
device pnp 2e.A on # Power Management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA onboard
|
||||
end
|
||||
device pci 13.0 on end # USB
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/model_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default CONFIG_ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
default CONFIG_PCI_ROM_RUN=1
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=0
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=5
|
||||
default CONFIG_PIRQ_ROUTE=1
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CONFIG_CROSS_COMPILE=""
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## CONFIG_DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
default CONFIG_VIDEO_MB = 0
|
||||
|
||||
end
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
arch i386 end
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_PIRQ_TABLE
|
||||
object irq_tables.o
|
||||
end
|
||||
# Compile cache_as_ram.c to auto.inc.
|
||||
makerule ./cache_as_ram_auto.inc
|
||||
# depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
|
||||
depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
# mainboardinit ./failover.inc
|
||||
end
|
||||
mainboardinit cpu/x86/fpu_enable.inc
|
||||
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
|
||||
mainboardinit ./cache_as_ram_auto.inc
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/lx
|
||||
device pci_domain 0 on
|
||||
device pci 1.0 on end # Northbridge
|
||||
device pci 1.1 on end # Graphics
|
||||
chip southbridge/amd/cs5536
|
||||
# IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
|
||||
# SIRQ Mode = Active(Quiet) mode. Save power....
|
||||
# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
|
||||
register "lpc_serirq_enable" = "0x0000105a"
|
||||
register "lpc_serirq_polarity" = "0x0000EFA5"
|
||||
register "lpc_serirq_mode" = "1"
|
||||
register "enable_gpio_int_route" = "0x0D0C0700"
|
||||
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
|
||||
register "enable_USBP4_device" = "1" # 0: host, 1:device
|
||||
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
|
||||
register "com1_enable" = "0"
|
||||
register "com1_address" = "0x3F8"
|
||||
register "com1_irq" = "4"
|
||||
register "com2_enable" = "0"
|
||||
register "com2_address" = "0x2F8"
|
||||
register "com2_irq" = "3"
|
||||
register "unwanted_vpci[0]" = "0" # End of list has a zero
|
||||
device pci 9.0 on end # Slot1
|
||||
device pci a.0 on end # Slot2
|
||||
device pci b.0 on end # Slot3
|
||||
device pci c.0 on end # Slot4
|
||||
device pci e.0 on end # Ethernet 0
|
||||
device pci 10.0 on end # Ethernet 1
|
||||
device pci 11.0 on end # SATA
|
||||
device pci f.0 on # ISA Bridge
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GAME_MIDI_GIPO1
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b off end # HW Monitor
|
||||
end
|
||||
end
|
||||
device pci f.2 on end # IDE Controller
|
||||
device pci f.3 on end # Audio
|
||||
device pci f.4 on end # OHCI
|
||||
device pci f.5 on end # EHCI
|
||||
end
|
||||
end
|
||||
# APIC cluster is late CPU init.
|
||||
device apic_cluster 0 on
|
||||
chip cpu/amd/model_lx
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_ARCH
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
uses CONFIG_COMPRESS
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_OBJCOPY
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_UDELAY_IO
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_VIDEO_MB
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_PIRQ_ROUTE
|
||||
|
||||
default CONFIG_ROM_SIZE = 256 * 1024
|
||||
default CONFIG_CONSOLE_VGA = 0
|
||||
default CONFIG_VIDEO_MB = 8
|
||||
default CONFIG_PCI_ROM_RUN = 0
|
||||
default CONFIG_HAVE_FALLBACK_BOOT = 1
|
||||
default CONFIG_GENERATE_MP_TABLE = 0
|
||||
default CONFIG_HAVE_HARD_RESET = 0
|
||||
default CONFIG_UDELAY_IO = 1
|
||||
default CONFIG_GENERATE_PIRQ_TABLE = 1
|
||||
default CONFIG_IRQ_SLOT_COUNT = 9
|
||||
default CONFIG_PIRQ_ROUTE = 1
|
||||
default CONFIG_HAVE_OPTION_TABLE = 0
|
||||
default CONFIG_ROM_IMAGE_SIZE = 32 * 1024
|
||||
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
|
||||
default CONFIG_USE_DCACHE_RAM = 1
|
||||
default CONFIG_DCACHE_RAM_BASE = 0xc8000
|
||||
default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
default CONFIG_STACK_SIZE = 8 * 1024
|
||||
default CONFIG_HEAP_SIZE = 16 * 1024
|
||||
# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
default CONFIG_USE_OPTION_TABLE = 0
|
||||
default CONFIG_RAMBASE = 0x00004000
|
||||
default CONFIG_ROM_PAYLOAD = 1
|
||||
default CONFIG_CROSS_COMPILE = ""
|
||||
default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC = "gcc"
|
||||
default CONFIG_CONSOLE_SERIAL8250 = 1
|
||||
default CONFIG_TTYS0_BAUD = 115200
|
||||
default CONFIG_TTYS0_BASE = 0x3f8
|
||||
default CONFIG_TTYS0_LCS = 0x3
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
|
@ -1,228 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
##
|
||||
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
|
||||
##
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
##
|
||||
## Image size calculation
|
||||
##
|
||||
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
driver rtl8168.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object fadt.o
|
||||
object acpi_tables.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dsdt.asl"
|
||||
action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl"
|
||||
action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl"
|
||||
action "mv $(CURDIR)/dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
ldscript /cpu/x86/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
mainboardinit cpu/intel/model_106cx/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i945
|
||||
|
||||
device apic_cluster 0 on
|
||||
chip cpu/intel/socket_441
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device pci_domain 0 on
|
||||
device pci 00.0 on end # host bridge
|
||||
device pci 01.0 off end # i945 PCIe root port
|
||||
device pci 02.0 on end # vga controller
|
||||
device pci 02.1 on end # display controller
|
||||
|
||||
chip southbridge/intel/i82801gx
|
||||
register "pirqa_routing" = "0x05"
|
||||
register "pirqb_routing" = "0x07"
|
||||
register "pirqc_routing" = "0x05"
|
||||
register "pirqd_routing" = "0x07"
|
||||
register "pirqe_routing" = "0x80"
|
||||
register "pirqf_routing" = "0x80"
|
||||
register "pirqg_routing" = "0x80"
|
||||
register "pirqh_routing" = "0x06"
|
||||
|
||||
# GPI routing
|
||||
# 0 No effect (default)
|
||||
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
|
||||
# 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
register "gpi13_routing" = "1"
|
||||
register "gpe0_en" = "0x20000601"
|
||||
|
||||
register "ide_legacy_combined" = "0x1"
|
||||
register "ide_enable_primary" = "0x1"
|
||||
register "ide_enable_secondary" = "0x0"
|
||||
register "sata_ahci" = "0x0"
|
||||
|
||||
device pci 1b.0 on end # High Definition Audio
|
||||
device pci 1c.0 on end # PCIe
|
||||
device pci 1c.1 on end # PCIe
|
||||
device pci 1c.2 on end # PCIe
|
||||
#device pci 1c.3 off end # PCIe port 4
|
||||
#device pci 1c.4 off end # PCIe port 5
|
||||
#device pci 1c.5 off end # PCIe port 6
|
||||
device pci 1d.0 on end # USB UHCI
|
||||
device pci 1d.1 on end # USB UHCI
|
||||
device pci 1d.2 on end # USB UHCI
|
||||
device pci 1d.3 on end # USB UHCI
|
||||
device pci 1d.7 on end # USB2 EHCI
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
#device pci 1e.2 off end # AC'97 Audio
|
||||
#device pci 1e.3 off end # AC'97 Modem
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/smsc/lpc47m15x
|
||||
device pnp 2e.0 off # Floppy
|
||||
end
|
||||
device pnp 2e.3 off # Parport
|
||||
end
|
||||
device pnp 2e.4 on
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.5 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
|
||||
end
|
||||
device pnp 2e.7 on # Keyboard+Mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
irq 0xf0 = 0x82 # HW accel A20.
|
||||
end
|
||||
device pnp 2e.8 on # GAME
|
||||
# all default
|
||||
end
|
||||
device pnp 2e.a on # PME
|
||||
end
|
||||
device pnp 2e.b on # MPU
|
||||
end
|
||||
end
|
||||
end
|
||||
#device pci 1f.1 off end # IDE
|
||||
device pci 1f.2 on end # SATA
|
||||
device pci 1f.3 on end # SMBus
|
||||
#device pci 1f.4 off end # Realtek ID Codec
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1,329 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007-2008 coresystems GmbH
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
# Tables
|
||||
uses CONFIG_GENERATE_MP_TABLE
|
||||
uses CONFIG_GENERATE_PIRQ_TABLE
|
||||
uses CONFIG_IRQ_SLOT_COUNT
|
||||
uses CONFIG_HAVE_OPTION_TABLE
|
||||
uses CONFIG_USE_OPTION_TABLE
|
||||
uses CONFIG_LB_CKS_RANGE_START
|
||||
uses CONFIG_LB_CKS_RANGE_END
|
||||
uses CONFIG_LB_CKS_LOC
|
||||
uses CONFIG_GENERATE_ACPI_TABLES
|
||||
uses CONFIG_HAVE_ACPI_RESUME
|
||||
uses CONFIG_HAVE_MAINBOARD_RESOURCES
|
||||
# SMP
|
||||
uses CONFIG_SMP
|
||||
uses CONFIG_LOGICAL_CPUS
|
||||
uses CONFIG_AP_IN_SIPI_WAIT
|
||||
uses CONFIG_MAX_CPUS
|
||||
uses CONFIG_MAX_PHYSICAL_CPUS
|
||||
uses CONFIG_IOAPIC
|
||||
# Image Size
|
||||
uses CONFIG_USE_FALLBACK_IMAGE
|
||||
uses CONFIG_HAVE_FALLBACK_BOOT
|
||||
uses CONFIG_FALLBACK_SIZE
|
||||
uses CONFIG_ROM_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_IMAGE_SIZE
|
||||
uses CONFIG_ROM_SECTION_SIZE
|
||||
uses CONFIG_ROM_SECTION_OFFSET
|
||||
# Payload
|
||||
uses CONFIG_ROM_PAYLOAD
|
||||
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
|
||||
uses CONFIG_PRECOMPRESSED_PAYLOAD
|
||||
# Build Internals
|
||||
uses CONFIG_RAMBASE
|
||||
uses CONFIG_ROMBASE
|
||||
uses CONFIG_STACK_SIZE
|
||||
uses CONFIG_HEAP_SIZE
|
||||
uses CONFIG_USE_DCACHE_RAM
|
||||
uses CONFIG_DCACHE_RAM_BASE
|
||||
uses CONFIG_DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
uses CONFIG_XIP_ROM_BASE
|
||||
uses CONFIG_XIP_ROM_SIZE
|
||||
uses CONFIG_HAVE_HARD_RESET
|
||||
uses CONFIG_HAVE_SMI_HANDLER
|
||||
uses CONFIG_PCIE_CONFIGSPACE_HOLE
|
||||
uses CONFIG_MMCONF_SUPPORT
|
||||
uses CONFIG_MMCONF_BASE_ADDRESS
|
||||
uses CONFIG_GFXUMA
|
||||
|
||||
#
|
||||
uses CONFIG_MAINBOARD
|
||||
uses CONFIG_MAINBOARD_PART_NUMBER
|
||||
uses CONFIG_MAINBOARD_VENDOR
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
|
||||
uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
|
||||
# Timers
|
||||
uses CONFIG_UDELAY_LAPIC
|
||||
# Console
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses CONFIG_TTYS0_BAUD
|
||||
uses CONFIG_TTYS0_BASE
|
||||
uses CONFIG_TTYS0_LCS
|
||||
uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_VGA
|
||||
uses CONFIG_VGA_ROM_RUN
|
||||
uses CONFIG_PCI_ROM_RUN
|
||||
uses CONFIG_DEBUG
|
||||
# Toolchain
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses CONFIG_CROSS_COMPILE
|
||||
uses CONFIG_OBJCOPY
|
||||
# Tweaks
|
||||
uses CONFIG_GDB_STUB
|
||||
uses CONFIG_MAX_REBOOT_CNT
|
||||
uses CONFIG_USE_WATCHDOG_ON_BOOT
|
||||
uses COREBOOT_EXTRA_VERSION
|
||||
uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
##
|
||||
default CONFIG_MAX_REBOOT_CNT=3
|
||||
|
||||
##
|
||||
## Use the watchdog to break out of a lockup condition
|
||||
##
|
||||
default CONFIG_USE_WATCHDOG_ON_BOOT=0
|
||||
|
||||
##
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
##
|
||||
default CONFIG_ROM_SIZE=CONFIG_FALLBACK_SIZE*2
|
||||
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default CONFIG_HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_LAPIC=1
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from coreboot
|
||||
##
|
||||
default CONFIG_HAVE_HARD_RESET=1
|
||||
|
||||
##
|
||||
## Build SMI handler
|
||||
##
|
||||
default CONFIG_HAVE_SMI_HANDLER=1
|
||||
|
||||
##
|
||||
## Leave a hole for mmapped PCIe config space
|
||||
##
|
||||
|
||||
default CONFIG_PCIE_CONFIGSPACE_HOLE=1
|
||||
default CONFIG_MMCONF_SUPPORT=1
|
||||
default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
|
||||
##
|
||||
## UMA
|
||||
##
|
||||
default CONFIG_GFXUMA=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default CONFIG_GENERATE_PIRQ_TABLE=1
|
||||
default CONFIG_IRQ_SLOT_COUNT=18
|
||||
|
||||
##
|
||||
## Build code to export an x86 MP table
|
||||
## Useful for specifying IRQ routing values
|
||||
##
|
||||
default CONFIG_GENERATE_MP_TABLE=1
|
||||
|
||||
##
|
||||
## Build code to provide ACPI support
|
||||
##
|
||||
default CONFIG_GENERATE_ACPI_TABLES=1
|
||||
default CONFIG_HAVE_MAINBOARD_RESOURCES=1
|
||||
default CONFIG_HAVE_ACPI_RESUME=1
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default CONFIG_HAVE_OPTION_TABLE=1
|
||||
|
||||
##
|
||||
## Move the default CONFIG_coreboot cmos range off of AMD RTC registers
|
||||
##
|
||||
default CONFIG_LB_CKS_RANGE_START=49
|
||||
default CONFIG_LB_CKS_RANGE_END=122
|
||||
default CONFIG_LB_CKS_LOC=123
|
||||
|
||||
#VGA Console
|
||||
default CONFIG_CONSOLE_VGA=1
|
||||
# There are some network option roms that don't work with
|
||||
# coreboot's x86emu. Thus, we only execute the VGA option rom
|
||||
# for now:
|
||||
default CONFIG_VGA_ROM_RUN=1
|
||||
default CONFIG_PCI_ROM_RUN=0
|
||||
default CONFIG_DEBUG=0
|
||||
|
||||
##
|
||||
## Build code for SMP support
|
||||
## Only worry about 2 micro processors
|
||||
##
|
||||
default CONFIG_SMP=1
|
||||
default CONFIG_MAX_CPUS=4
|
||||
default CONFIG_MAX_PHYSICAL_CPUS=2
|
||||
default CONFIG_LOGICAL_CPUS=1
|
||||
default CONFIG_AP_IN_SIPI_WAIT=1
|
||||
|
||||
##
|
||||
## enable CACHE_AS_RAM specifics
|
||||
##
|
||||
default CONFIG_USE_DCACHE_RAM=1
|
||||
default CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
default CONFIG_DCACHE_RAM_BASE=0xffed8000
|
||||
default CONFIG_USE_PRINTK_IN_CAR=1
|
||||
|
||||
##
|
||||
## Execute In Place settings
|
||||
##
|
||||
|
||||
default CONFIG_XIP_ROM_SIZE = 128 * 1024
|
||||
default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
|
||||
|
||||
##
|
||||
## Build code to setup a generic IOAPIC
|
||||
##
|
||||
default CONFIG_IOAPIC=1
|
||||
|
||||
##
|
||||
## Clean up the motherboard id strings
|
||||
##
|
||||
default CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
default CONFIG_MAINBOARD_VENDOR= "INTEL"
|
||||
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
|
||||
default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x464c
|
||||
|
||||
###
|
||||
### coreboot layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
|
||||
default CONFIG_ROM_IMAGE_SIZE = 0xb800
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default CONFIG_STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 32K heap
|
||||
##
|
||||
default CONFIG_HEAP_SIZE=0x8000
|
||||
|
||||
|
||||
###
|
||||
### Compute the location and size of where this firmware image
|
||||
### (coreboot plus bootloader) will live in the boot rom chip.
|
||||
###
|
||||
default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
|
||||
|
||||
##
|
||||
## coreboot C code runs at this location in RAM
|
||||
##
|
||||
default CONFIG_RAMBASE=0x00100000
|
||||
|
||||
##
|
||||
## Load the payload from the ROM
|
||||
##
|
||||
default CONFIG_ROM_PAYLOAD=1
|
||||
|
||||
###
|
||||
### Defaults of options that you may want to override in the target config file
|
||||
###
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## Disable the gdb stub by default
|
||||
##
|
||||
default CONFIG_GDB_STUB=0
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default CONFIG_TTYS0_BAUD=115200
|
||||
#default CONFIG_TTYS0_BAUD=57600
|
||||
#default CONFIG_TTYS0_BAUD=38400
|
||||
#default CONFIG_TTYS0_BAUD=19200
|
||||
#default CONFIG_TTYS0_BAUD=9600
|
||||
#default CONFIG_TTYS0_BAUD=4800
|
||||
#default CONFIG_TTYS0_BAUD=2400
|
||||
#default CONFIG_TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default CONFIG_TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the coreboot loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
|
||||
## At a maximum only compile in this level of debugging
|
||||
default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
|
||||
|
||||
##
|
||||
## Select power on after power fail setting
|
||||
default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
|
||||
|
||||
### End Options.lb
|
||||
end
|
||||
|
|
@ -1,212 +0,0 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or
|
||||
## modify it under the terms of the GNU General Public License as
|
||||
## published by the Free Software Foundation; version 2 of
|
||||
## the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
## MA 02110-1301 USA
|
||||
##
|
||||
|
||||
##
|
||||
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
|
||||
##
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
|
||||
|
||||
## CONFIG_XIP_ROM_SIZE must be a power of 2.
|
||||
default CONFIG_XIP_ROM_SIZE = 64 * 1024
|
||||
include /config/nofailovercalculation.lb
|
||||
|
||||
##
|
||||
## Set all of the defaults for an x86 architecture
|
||||
##
|
||||
|
||||
arch i386 end
|
||||
|
||||
##
|
||||
## Build the objects we have code for in this directory.
|
||||
##
|
||||
|
||||
driver mainboard.o
|
||||
if CONFIG_GENERATE_MP_TABLE object mptable.o end
|
||||
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
|
||||
|
||||
if CONFIG_GENERATE_ACPI_TABLES
|
||||
object fadt.o
|
||||
object acpi_tables.o
|
||||
makerule dsdt.c
|
||||
depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
|
||||
action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
|
||||
action "mv $(CURDIR)/dsdt.hex dsdt.c"
|
||||
end
|
||||
object ./dsdt.o
|
||||
end
|
||||
|
||||
if CONFIG_HAVE_HARD_RESET object reset.o end
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
|
||||
makerule ./auto.o
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
|
||||
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
|
||||
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
|
||||
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
if CONFIG_USE_INIT
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
ldscript /cpu/x86/car/cache_as_ram.lds
|
||||
end
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Setup Cache-As-Ram
|
||||
##
|
||||
## Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
|
||||
mainboardinit cpu/intel/model_6ex/cache_as_ram.inc
|
||||
|
||||
###
|
||||
### This is the early phase of coreboot startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
if CONFIG_USE_INIT
|
||||
initobject auto.o
|
||||
else
|
||||
mainboardinit ./auto.inc
|
||||
end
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/intel/i3100
|
||||
device pci_domain 0 on
|
||||
device pci 00.0 on end # IMCH
|
||||
device pci 00.1 on end # IMCH error status
|
||||
device pci 01.0 on end # IMCH EDMA engine
|
||||
device pci 02.0 on end # PCIe port A/A0
|
||||
device pci 03.0 on end # PCIe port A1
|
||||
chip southbridge/intel/i3100
|
||||
# PIRQ line -> legacy IRQ mappings
|
||||
register "pirq_a_d" = "0x8b808a8a"
|
||||
register "pirq_e_h" = "0x85808080"
|
||||
|
||||
device pci 1c.0 on end # PCIe port B0
|
||||
device pci 1c.1 off end # PCIe port B1
|
||||
device pci 1c.2 off end # PCIe port B2
|
||||
device pci 1c.3 off end # PCIe port B3
|
||||
device pci 1d.0 on end # USB (UHCI) 1
|
||||
device pci 1d.1 on end # USB (UHCI) 2
|
||||
device pci 1d.7 on end # USB (EHCI)
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # LPC bridge
|
||||
chip superio/intel/i3100
|
||||
device pnp 4e.4 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.5 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end
|
||||
chip superio/smsc/smscsuperio
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.2 off # Serial Port 4
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 off # Serial Port 3
|
||||
io 0x60 = 0x3e8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # PS/2 Keyboard / Mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 2e.a off # Runtime registers
|
||||
io 0x60 = 0x600
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on end # SATA
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.4 on end # Performance counters
|
||||
end
|
||||
end
|
||||
device apic_cluster 0 on
|
||||
chip cpu/intel/bga956
|
||||
device apic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue