From abd0f60298cff49a68492f3c4e6304ae6159d0f9 Mon Sep 17 00:00:00 2001
From: Yidi Lin <yidilin@chromium.org>
Date: Wed, 19 Mar 2025 17:59:36 +0800
Subject: [PATCH] soc/mediatek/common: Add rtc_mt6359p.h for SoCs using mt6359p
 RTC

MT8188, MT8192 and MT8195 use mt6359p RTC and share the same RTC
definitions. Move the definitions to rtc_mt6359p.h and remove duplicate
definitions.

BUG=b:391067089
TEST=build coreboot for asurada, cherry and geralt

Change-Id: I6e60148e1847171c6ab6b6dbee2fd706f3c3a47f
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 .../mediatek/common/include/soc/rtc_mt6359p.h | 81 +++++++++++++++++++
 src/soc/mediatek/mt8188/include/soc/rtc.h     | 76 +----------------
 src/soc/mediatek/mt8192/include/soc/rtc.h     | 77 +-----------------
 src/soc/mediatek/mt8195/include/soc/rtc.h     | 77 +-----------------
 4 files changed, 84 insertions(+), 227 deletions(-)
 create mode 100644 src/soc/mediatek/common/include/soc/rtc_mt6359p.h

diff --git a/src/soc/mediatek/common/include/soc/rtc_mt6359p.h b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
new file mode 100644
index 0000000000..fcae61e914
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/rtc_mt6359p.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
+
+#ifndef SOC_MEDIATEK_RTC_MT6359P_H
+#define SOC_MEDIATEK_RTC_MT6359P_H
+
+/* RTC registers */
+enum {
+	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
+	RTC_BBPU_SPAR_SW	= 1U << 1,
+	RTC_BBPU_RESET_SPAR	= 1U << 2,
+	RTC_BBPU_RESET_ALARM	= 1U << 3,
+	RTC_BBPU_CLRPKY	= 1U << 4,
+	RTC_BBPU_RELOAD	= 1U << 5,
+	RTC_BBPU_CBUSY	= 1U << 6,
+	RTC_CBUSY_TIMEOUT_US = 1000000,
+};
+
+enum {
+	RTC_XOSCCALI_MASK	= 0x1F << 0,
+	RTC_XOSC32_ENB		= 1U << 5,
+	RTC_EMB_HW_MODE		= 0U << 6,
+	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
+	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
+	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
+	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
+	RTC_EMBCK_SRC_SEL	= 1U << 8,
+	RTC_EMBCK_SEL_OPTION	= 1U << 9,
+	RTC_GPS_CKOUT_EN	= 1U << 10,
+	RTC_EOSC32_VCT_EN	= 1U << 11,
+	RTC_EOSC32_CHOP_EN	= 1U << 12,
+	RTC_GP_OSC32_CON	= 2U << 13,
+	RTC_REG_XOSC32_ENB	= 1U << 15,
+};
+
+enum {
+	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
+		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
+		RTC_EMB_K_EOSC32_MODE,
+};
+
+enum {
+	PMIC_RG_BANK_FQMTR_RST = 0x522,
+};
+
+enum {
+	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
+	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
+};
+
+/* PMIC frequency meter definition */
+enum {
+	PMIC_RG_FQMTR_CKSEL	= 0x0118,
+	PMIC_RG_FQMTR_RST	= 0x013A,
+	PMIC_RG_FQMTR_CON0	= 0x0546,
+	PMIC_RG_FQMTR_WINSET	= 0x0548,
+	PMIC_RG_FQMTR_DATA	= 0x054A,
+	FQMTR_TIMEOUT_US	= 8000,
+};
+
+enum {
+	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
+	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
+	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
+	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
+	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
+	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
+	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
+	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
+};
+
+enum {
+	RTC_TC_MTH_MASK = 0xf,
+};
+
+enum {
+	RTC_K_EOSC_RSV_0	= 1 << 8,
+	RTC_K_EOSC_RSV_1	= 1 << 9,
+	RTC_K_EOSC_RSV_2	= 1 << 10,
+};
+
+#endif /* SOC_MEDIATEK_RTC_MT6359P_H */
diff --git a/src/soc/mediatek/mt8188/include/soc/rtc.h b/src/soc/mediatek/mt8188/include/soc/rtc.h
index 7947f346cf..5278aff5e4 100644
--- a/src/soc/mediatek/mt8188/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8188/include/soc/rtc.h
@@ -5,82 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC frequency meter definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8188_RTC_H */
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
index 0df519f15f..ee06801869 100644
--- a/src/soc/mediatek/mt8192/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -5,83 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC Frequency Meter Definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8192_RTC_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/rtc.h b/src/soc/mediatek/mt8195/include/soc/rtc.h
index 3210ac1be2..a2c066d481 100644
--- a/src/soc/mediatek/mt8195/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8195/include/soc/rtc.h
@@ -5,83 +5,8 @@
 
 #include <soc/pmif.h>
 #include <soc/rtc_common.h>
+#include <soc/rtc_mt6359p.h>
 #include <soc/rtc_reg_common.h>
 #include <stdbool.h>
 
-/* RTC registers */
-enum {
-	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
-	RTC_BBPU_SPAR_SW	= 1U << 1,
-	RTC_BBPU_RESET_SPAR	= 1U << 2,
-	RTC_BBPU_RESET_ALARM	= 1U << 3,
-	RTC_BBPU_CLRPKY	= 1U << 4,
-	RTC_BBPU_RELOAD	= 1U << 5,
-	RTC_BBPU_CBUSY	= 1U << 6,
-	RTC_CBUSY_TIMEOUT_US = 1000000,
-};
-
-enum {
-	RTC_XOSCCALI_MASK	= 0x1F << 0,
-	RTC_XOSC32_ENB		= 1U << 5,
-	RTC_EMB_HW_MODE		= 0U << 6,
-	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
-	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
-	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
-	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
-	RTC_EMBCK_SRC_SEL	= 1U << 8,
-	RTC_EMBCK_SEL_OPTION	= 1U << 9,
-	RTC_GPS_CKOUT_EN	= 1U << 10,
-	RTC_EOSC32_VCT_EN	= 1U << 11,
-	RTC_EOSC32_CHOP_EN	= 1U << 12,
-	RTC_GP_OSC32_CON	= 2U << 13,
-	RTC_REG_XOSC32_ENB	= 1U << 15,
-};
-
-enum {
-	OSC32CON_ANALOG_SETTING = RTC_GP_OSC32_CON | RTC_EOSC32_CHOP_EN |
-		RTC_EOSC32_VCT_EN | RTC_GPS_CKOUT_EN | RTC_EMBCK_SEL_OPTION |
-		RTC_EMB_K_EOSC32_MODE,
-};
-
-enum {
-	PMIC_RG_BANK_FQMTR_RST = 0x522,
-};
-
-enum {
-	PMIC_RG_FQMTR_DCXO26M_EN_SHIFT = 4,
-	PMIC_RG_BANK_FQMTR_RST_SHIFT = 6,
-};
-
-/* PMIC Frequency Meter Definition */
-enum {
-	PMIC_RG_FQMTR_CKSEL	= 0x0118,
-	PMIC_RG_FQMTR_RST	= 0x013A,
-	PMIC_RG_FQMTR_CON0	= 0x0546,
-	PMIC_RG_FQMTR_WINSET	= 0x0548,
-	PMIC_RG_FQMTR_DATA	= 0x054A,
-	FQMTR_TIMEOUT_US	= 8000,
-};
-
-enum {
-	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
-	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
-	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
-	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
-	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
-	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
-	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
-	PMIC_FQMTR_CKSEL_MASK		= 7U << 0,
-};
-
-
-enum {
-	RTC_TC_MTH_MASK = 0xf,
-};
-
-enum {
-	RTC_K_EOSC_RSV_0	= 1 << 8,
-	RTC_K_EOSC_RSV_1	= 1 << 9,
-	RTC_K_EOSC_RSV_2	= 1 << 10,
-};
-
 #endif /* SOC_MEDIATEK_MT8195_RTC_H */