Tweaks for VIA SPD support.
Added L2 cache support.
This commit is contained in:
Ronald G. Minnich
parent
db69e90633
commit
ab80324461
3 changed files with 959 additions and 1 deletions
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@ -29,7 +29,9 @@
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#include <southbridge/via/vt82c686/setup_serial.inc>
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#include <pc80/serial.inc>
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/*
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#include <pc80/i8259.inc>
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*/
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TTYS0_TX_STRING($ttyS0_test)
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931
src/cpu/p6/l2_cache.c
Normal file
931
src/cpu/p6/l2_cache.c
Normal file
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@ -0,0 +1,931 @@
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/* $Id$
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*
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* Copyright : (c) 2000 by Denis Dowling (dpd@alphalink.com.au)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Description :
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* Intel Pentium L2 Cache initialization.
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* This code was developed by reversing engineering
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* the BIOS. Where the code accesses documented
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* registers I have added comments as best I can.
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* Some undocumented registers on the PentiumII are
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* used so some of the documentation is incomplete
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*
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* References:
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* Intel Architecture Software Developer's Manual
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* Volume 3: System Programming
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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/* Include debugging code and outputs */
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#define DEBUG
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static int signal_l2(unsigned int address_high,
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unsigned int address_low,
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unsigned int data_high,
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unsigned int data_low,
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int way, int command);
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static int read_l2(unsigned int address);
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static int write_l2(unsigned int address, int data);
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static int write_l2_2(unsigned int address,
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unsigned int data1,
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unsigned int data2);
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static int test_l2_address_alias(unsigned int address1,
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unsigned int address2,
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unsigned int data_high,
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unsigned int data_low);
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static int calculate_l2_latency(void);
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static int set_l2_register4(int l);
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static int calculate_l2_cache_size(void);
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static int calculate_l2_physical_address_range(void);
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static int calculate_l2_ecc(void);
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#ifdef DEBUG
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#define DBG(x...) printk(KERN_DEBUG x)
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#else
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#define DBG(x...)
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#endif
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static void cache_disable(void)
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{
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unsigned int tmp;
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/* Disable cache */
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/* Write back the cache and flush TLB */
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asm volatile ("movl %%cr0, %0\n\t"
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"orl $0x40000000, %0\n\t"
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"wbinvd\n\t"
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"movl %0, %%cr0\n\t"
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"wbinvd\n\t"
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: "=r" (tmp) : : "memory");
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}
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static void cache_enable(void)
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{
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unsigned int tmp;
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asm volatile ("movl %%cr0, %0\n\t"
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"andl $0x9fffffff, %0\n\t"
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"movl %0, %%cr0\n\t"
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: "=r" (tmp) : : "memory");
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}
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int intel_l2_configure()
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{
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unsigned int eax, ebx, ecx, edx;
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int signature, tmp;
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int cache_size;
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cpuid(0, &eax, &ebx, &ecx, &edx);
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if (ebx != 0x756e6547 ||
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edx != 0x49656e69 ||
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ecx != 0x6c65746e)
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{
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printk(KERN_ERR "Not 'GenuineIntel' Processor\n");
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return -1;
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}
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cpuid(1, &eax, &ebx, &ecx, &edx);
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/* Mask out the stepping */
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signature = eax & 0xfff0;
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if (signature & 0x1000)
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{
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DBG("Overdrive chip no L2 cache configuration\n");
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return 0;
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}
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if (signature < 0x630 || signature >= 0x680)
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{
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DBG("CPU signature of %x so no need for L2 cache configuration\n",
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signature);
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return 0;
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}
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* If bit 23 (L2 Hardware disable is set then done */
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if (eax & 0x800000)
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{
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DBG("L2 Hardware disabled\n");
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return 0;
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}
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if (signature == 0x630)
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{
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/* 0x630 signature setup */
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/* Read EBL_CR_POWERON */
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rdmsr(0x2a, eax, edx);
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/* Mask out [22-24] Clock frequency ratio */
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eax &= 0x1c00000;
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if (eax == 0xc00000 || eax == 0x1000000)
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{
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printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
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return -1;
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}
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* Mask out:
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* [0] L2 Configured
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* [5] ECC Check Enable
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* [6] Address Parity Check Enable
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* [7] CRTN Parity Check Enable
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* [8] L2 Enabled
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* [12:11] Number of L2 banks
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* [17:13] Cache size per bank
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* [18] Cache state error checking enable
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* [22:20] L2 Physical Address Range Support
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*/
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eax &= 0xff88061e;
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/* Set:
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* [17:13] = 00010 = 512Kbyte Cache size per bank
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* [18] Cache state error checking enable
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*/
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eax |= 0x44000;
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/* Write BBL_CR_CTL3 */
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wrmsr(0x11e, eax, edx);
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}
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else
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{
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int calc_eax;
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int v;
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/* After 0x630 signature setup */
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/* Read EBL_CR_POWERON */
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rdmsr(0x2a, eax, edx);
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/* Mask out [22-24] Clock frequency ratio */
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eax &= 0x3c00000;
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if (eax == 0xc00000 || eax == 0x3000000)
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{
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printk(KERN_ERR "Incorrect clock frequency ratio %x\n", eax);
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return -1;
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}
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* Mask out:
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* [0] L2 Configured
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* [5] ECC Check Enable
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* [6] Address Parity Check Enable
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* [7] CRTN Parity Check Enable
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* [8] L2 Enabled
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* [12:11] Number of L2 banks
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* [17:13] Cache size per bank
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* [18] Cache state error checking enable
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* [22:20] L2 Physical Address Range Support
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*/
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eax &= 0xff88061e;
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/* Set:
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* [17:13] = 00000 = 128Kbyte Cache size per bank
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* [18] Cache state error checking enable
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*/
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eax |= 0x40000;
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/* Write BBL_CR_CTL3 */
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wrmsr(0x11e, eax, edx);
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/* Set the l2 latency in BBL_CR_CTL3 */
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if (calculate_l2_latency() != 0)
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return -1;
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/* Read the new latency values back */
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rdmsr(0x11e, calc_eax, edx);
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/* Write back the original default value */
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wrmsr(0x11e, eax, edx);
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/* Mask [27:26] out of BBL_CR_CTL3 - Reserved?? */
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v = calc_eax & 0xc000000;
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/* Shift to [1:0] */
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v >>= 26;
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DBG("Sending %x to set_l2_register4\n", v);
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if (set_l2_register4(v) != 0)
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return -1;
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/* Restore the correct latency value into BBL_CR_CTL3 */
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wrmsr(0x11e, calc_eax, edx);
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}
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/* Read L2 register 0 */
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tmp = read_l2(0);
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if (tmp < 0)
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{
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printk(KERN_ERR "Failed to read_l2(0)\n");
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return -1;
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}
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/* test if L2(0) has bit 0x20 set */
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if ((tmp & 0x20) != 0)
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{
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/* Read BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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/* Set bits [6-7] CRTN + Address Parity enable */
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eax |= 0xc0;
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/* Write BBL_CR_CTL3 */
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wrmsr(0x11e, eax, edx);
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}
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if (calculate_l2_ecc() != 0)
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{
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printk(KERN_ERR "Failed to calculate L2 ECC\n");
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return -1;
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}
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if (calculate_l2_physical_address_range() != 0)
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{
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printk(KERN_ERR "Failed to calculate L2 physical address range\n");
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return -1;
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}
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if (calculate_l2_cache_size() != 0)
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{
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printk(KERN_ERR "Failed to calculate L2 cache size\n");
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return -1;
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}
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/* Turn on cache. Only L1 is active at this time. */
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cache_enable();
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/* Get the calculated cache size from BBL_CR_CTL3 [17:13]*/
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rdmsr(0x11e, eax, edx);
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cache_size = (eax & 0x3e000);
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if (cache_size == 0)
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cache_size = 0x1000;
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cache_size = cache_size << 3;
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/* Cache is 4 way for each address */
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DBG("L2 Cache size is %dK\n", cache_size*4/1024);
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/* Write to all cache lines to initialize */
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while(cache_size > 0)
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{
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int way;
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/* Each Cache line in 32 bytes */
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cache_size -= 0x20;
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/* Update each way */
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for(way = 0; way < 4; way++)
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{
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/* Send Tag Write w/Data Write (TWW) to L2 controller
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* MESI = Invalid
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*/
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if (signal_l2(0, cache_size, 0, 0, way, 0x1c) != 0)
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{
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printk(KERN_ERR "Failed on signal_l2(%x, %x)\n",
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cache_size, way);
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return -1;
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}
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}
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}
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DBG("L2 Cache lines initialized\n");
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/* Disable cache */
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cache_disable();
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/* Set L2 cache configured in BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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eax |= 0x1;
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wrmsr(0x11e, eax, edx);
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/* Invalidate cache and discard unsaved writes */
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asm volatile("invd");
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/* Write 0 to L2 control register 5 */
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if (write_l2(5, 0) != 0)
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{
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printk(KERN_ERR "write_l2(5, 0) failed\n");
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return 0;
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}
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if (signature == 0x650 || signature == 0x670)
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{
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/* Change the L2 latency to 0101 then back to
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* original value. I don't know why this is needed - dpd
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*/
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int old_eax;
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rdmsr(0x11e, eax, edx);
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old_eax = eax;
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eax &= 0xffffffe1;
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eax |= 0x0000000a;
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wrmsr(0x11e, eax, edx);
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wrmsr(0x11e, old_eax, edx);
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}
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/* Set L2 enabled in BBL_CR_CTL3 */
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rdmsr(0x11e, eax, edx);
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eax |= 0x00000100;
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wrmsr(0x11e, eax, edx);
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/* Turn on cache. Both L1 and L2 are now active. Wahoo! */
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cache_enable();
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return 0;
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}
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/* Setup address_high:address_low, data_high:data_low into the L2
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* control registers and then issue command with correct cache way
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*/
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int signal_l2(unsigned int address_high, unsigned int address_low,
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unsigned int data_high, unsigned int data_low,
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int way, int command)
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{
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unsigned int eax, edx;
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int i;
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/* Write L2 Address to BBL_CR_ADDR */
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wrmsr(0x116, address_low, address_high);
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/* Write data to BBL_CR_D[0-3] */
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for(i = 0; i < 4; i++)
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wrmsr(0x88 + i, data_low, data_high);
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/* Put the command into BBL_CR_CTL */
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rdmsr(0x119, eax, edx);
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edx = 0;
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eax &= 0xfffffce0;
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eax |= command;
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eax |= way << 8;
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wrmsr(0x119, eax, edx);
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/* Write to BBL_CR_TRIG to trigger L2 controller */
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wrmsr(0x11a, 0, 0);
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/* Poll the controller to see when done */
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for(i = 0; i < 0x100; i++)
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{
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/* Read BBL_CR_BUSY */
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rdmsr(0x11b, eax, edx);
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/* If not busy then return */
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if ((eax & 1) == 0)
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return 0;
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}
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/* Return timeout code */
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return -1;
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}
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/* Read the L2 Cache controller register at given address */
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static int read_l2(unsigned int address)
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{
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unsigned int eax, edx;
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address = address << 5;
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/* Send a L2 Control Register Read to L2 controller */
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if (signal_l2(0, address, 0, 0, 0, 2) != 0)
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return -1;
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/* If OK then get the result from BBL_CR_ADDR */
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rdmsr(0x116, eax, edx);
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eax = eax >> 0x15;
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return eax;
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}
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/* data1 = eax, data2 = ebx */
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static int write_l2_2(unsigned int address,
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unsigned int data1,
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unsigned int data2)
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{
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data1 &= 0xff;
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data1 = data1 << 0x15;
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data2 = data2 << 0x0b;
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data2 &= 0x1800;
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data1 |= data2;
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data2 = data2 >> 6;
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data2 &= 0x20000;
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data1 |= data2;
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address = address << 5;
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address |= data1;
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/* L2 Control Register Write */
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return signal_l2(0, address, 0, 0, 0, 3);
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}
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/* Write data into the L2 controller register at address */
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static int write_l2(unsigned int address, int data)
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{
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int v1, v2, i;
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v1 = read_l2(0);
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if (v1 < 0)
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return -1;
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v2 = read_l2(2);
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if (v2 < 0)
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return -1;
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if ((v1 & 0x20) == 0)
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{
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v2 &= 0x3;
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v2++;
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}
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else
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v2 &= 0x7;
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for(i = 0; i < v2; i++)
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if (write_l2_2(address, data, i) != 0)
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return -1;
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return 0;
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}
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/* Write data_high:data_low into the cache at address1. Test address2
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* to see if the same data is returned. Return 0 if the data matches.
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* return lower 16 bits if mismatched data if mismatch. Return -1
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* on error
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*/
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static int test_l2_address_alias(unsigned int address1,
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unsigned int address2,
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unsigned int data_high,
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unsigned int data_low)
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{
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unsigned int eax, edx;
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int d;
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/* Tag Write with Data Write for L2 */
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if (signal_l2(0, address1, data_high, data_low, 0, 0x1c) != 0)
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return -1;
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/* Tag Read with Data Read for L2 */
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if (signal_l2(0, address2, 0, 0, 0, 0xe) != 0)
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return -1;
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/* Read data from BBL_CR_D[0-3] */
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for(d = 0x88; d <= 0x8b; d++)
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{
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rdmsr(d, eax, edx);
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if (eax != data_low || edx != data_high)
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||||
return (eax & 0xffff);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Latency Tables */
|
||||
struct latency_entry
|
||||
{
|
||||
unsigned char key;
|
||||
unsigned char value;
|
||||
};
|
||||
|
||||
static const struct latency_entry latency_650_t0[] =
|
||||
{
|
||||
{ 0x10, 0x02 }, { 0x50, 0x02 }, { 0x20, 0x04 }, { 0x60, 0x06 },
|
||||
{ 0x00, 0x08 }, { 0x40, 0x0C }, { 0x12, 0x06 }, { 0x52, 0x0A },
|
||||
{ 0x22, 0x0E }, { 0x62, 0x10 }, { 0x02, 0x10 }, { 0xFF, 0x00 }
|
||||
};
|
||||
|
||||
static const struct latency_entry latency_650_t1[] =
|
||||
{
|
||||
{ 0x12, 0x14 }, { 0x52, 0x16 }, { 0x22, 0x16 }, { 0x62, 0x16 },
|
||||
{ 0xFF, 0x00 }
|
||||
};
|
||||
|
||||
static const struct latency_entry latency_670_t0[] =
|
||||
{
|
||||
{ 0x60, 0x06 }, { 0x00, 0x08 }, { 0x12, 0x06 }, { 0x52, 0x0A },
|
||||
{ 0x22, 0x0E }, { 0x62, 0x10 }, { 0x02, 0x10 }, { 0x42, 0x02 },
|
||||
{ 0x11, 0x0E }, { 0x51, 0x0C }, { 0x21, 0x02 }, { 0x61, 0x10 },
|
||||
{ 0x01, 0x10 }, { 0x41, 0x02 }, { 0xFF, 0x00 }
|
||||
};
|
||||
|
||||
static const struct latency_entry latency_670_t1[] =
|
||||
{
|
||||
{ 0x22, 0x18 }, { 0x62, 0x18 }, { 0x02, 0x1A }, { 0x11, 0x18 },
|
||||
{ 0xFF, 0x00 }
|
||||
};
|
||||
|
||||
static const struct latency_entry latency_670_t2[] =
|
||||
{
|
||||
{ 0x22, 0x12 }, { 0x62, 0x14 }, { 0x02, 0x16 }, { 0x42, 0x1E },
|
||||
{ 0x11, 0x12 }, { 0x51, 0x16 }, { 0x21, 0x1E }, { 0x61, 0x14 },
|
||||
{ 0x01, 0x16 }, { 0x41, 0x1E }, { 0xFF, 0x00 }
|
||||
};
|
||||
|
||||
/* Latency tables for 650 model/type */
|
||||
static const struct latency_entry *latency_650[] =
|
||||
{
|
||||
latency_650_t0, latency_650_t1, latency_650_t1
|
||||
};
|
||||
|
||||
/* Latency tables for 670 model/type */
|
||||
static const struct latency_entry *latency_670[] =
|
||||
{
|
||||
latency_670_t0, latency_670_t1, latency_670_t2
|
||||
};
|
||||
|
||||
static int calculate_l2_latency(void)
|
||||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
int l;
|
||||
const struct latency_entry *latency_table, *le;
|
||||
|
||||
/* Read an undocumented MSR */
|
||||
rdmsr(0x17, eax, edx);
|
||||
|
||||
DBG("rdmsr(0x17) = %x, %x\n", eax, edx);
|
||||
|
||||
/* Mask out [23:20] in EDX. Are Intel trying to hide this?? */
|
||||
edx &= 0x1e00000;
|
||||
|
||||
if (edx != 0)
|
||||
{
|
||||
/* Get latency value directly from edx */
|
||||
l = edx >> 20;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Look up the latency from tables */
|
||||
int t, a;
|
||||
|
||||
/* Read L2 register 0 */
|
||||
a = read_l2(0);
|
||||
if (a < 0)
|
||||
return -1;
|
||||
|
||||
/* Mask out [7:4] */
|
||||
a &= 0xf0;
|
||||
|
||||
if ((a & 0x20) == 0)
|
||||
t = 0;
|
||||
else if (a == 0x20)
|
||||
t = 1;
|
||||
else if (a == 0x30)
|
||||
t = 2;
|
||||
else
|
||||
return -1;
|
||||
|
||||
cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
/* Mask out Model/Type */
|
||||
eax &= 0xfff0;
|
||||
|
||||
DBG("L2 latency type = %x\n", t);
|
||||
|
||||
if (eax == 0x650)
|
||||
{
|
||||
/* Read EBL_CR_POWERON */
|
||||
rdmsr(0x2a, eax, edx);
|
||||
|
||||
/* Mask [25:22] [19] Clock frequency Ratio & reserved */
|
||||
eax &= 0x3c80000;
|
||||
|
||||
/* Shift to [7:4] [1] */
|
||||
eax >>= 18;
|
||||
|
||||
latency_table = latency_650[t];
|
||||
}
|
||||
else if (eax == 0x670)
|
||||
{
|
||||
/* Read EBL_CR_POWERON */
|
||||
rdmsr(0x2a, eax, edx);
|
||||
|
||||
/* Mask [25:22] [19:18] Clock frequency Ratio & reserved */
|
||||
eax &= 0x3cc0000;
|
||||
|
||||
/* Shift to [7:4] [1:0] */
|
||||
eax >>= 18;
|
||||
|
||||
latency_table = latency_670[t];
|
||||
}
|
||||
else
|
||||
return -1;
|
||||
|
||||
DBG("Searching for key %x\n", eax);
|
||||
|
||||
/* Search table for matching entry */
|
||||
for(le = latency_table; le->key != eax; le++)
|
||||
{
|
||||
/* Fail if we get to the end of the table */
|
||||
if (le->key == 0xff)
|
||||
{
|
||||
printk(KERN_ERR "Could not find key %x in latency table\n",
|
||||
eax);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
l = le->value;
|
||||
}
|
||||
|
||||
DBG("L2 Cache latency is %d\n", l/2);
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* Mask out the latency */
|
||||
eax &= 0xffffffe1;
|
||||
|
||||
/* Or in the new value */
|
||||
eax |= l;
|
||||
|
||||
/* Write BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Pass some infomation into the L2 controller register 4*/
|
||||
static int set_l2_register4(int l)
|
||||
{
|
||||
int a;
|
||||
|
||||
/* Mask out all but lower 2 bits in l */
|
||||
l &= 3;
|
||||
|
||||
/* Read L2 register 4 */
|
||||
a = read_l2(4);
|
||||
if (a < 0)
|
||||
return -1;
|
||||
|
||||
/* Mask off the lower 2 bits */
|
||||
a &= 0xfffc;
|
||||
|
||||
/* Or in the new latency */
|
||||
a |= l;
|
||||
|
||||
/* Write L2 register 4 */
|
||||
if (write_l2(4, a) != 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int calculate_l2_cache_size(void)
|
||||
{
|
||||
unsigned int eax, edx;
|
||||
int v;
|
||||
|
||||
v = read_l2(0);
|
||||
if (v < 0)
|
||||
return -1;
|
||||
if ((v & 0x20) == 0)
|
||||
{
|
||||
unsigned int cache_setting;
|
||||
int v;
|
||||
unsigned int address, size;
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* Check sizes from 256KB up to 4MB */
|
||||
for(cache_setting = 0x2000;
|
||||
cache_setting <= 0x20000;
|
||||
cache_setting <<= 1)
|
||||
{
|
||||
unsigned int new_eax;
|
||||
|
||||
/* Mask out the cache size */
|
||||
eax &= 0xfffc1fff;
|
||||
|
||||
/* Or in the current setting */
|
||||
eax |= cache_setting;
|
||||
|
||||
new_eax = eax;
|
||||
|
||||
/* Write new value into BBL_CR_CTL3 and read it back */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* If the value didn't change then break */
|
||||
if (eax != new_eax)
|
||||
break;
|
||||
}
|
||||
|
||||
/* Reset to the last value that worked */
|
||||
cache_setting >>= 1;
|
||||
|
||||
/* Mask to just the cache setting bits */
|
||||
cache_setting &= 0x3e000;
|
||||
|
||||
/* Mask out cache size from eax */
|
||||
eax &= 0xfffc1fff;
|
||||
|
||||
/* Or in the correct setting */
|
||||
eax |= cache_setting;
|
||||
|
||||
/* Write new value into BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
DBG("Maximum cache mask is %x\n", cache_setting);
|
||||
|
||||
/* Write aaaaaaaa:aaaaaaaa to address 0 in the l2 cache */
|
||||
v = test_l2_address_alias(0, 0, 0xaaaaaaaa, 0xaaaaaaaa);
|
||||
if (v != 0)
|
||||
return -1;
|
||||
|
||||
size = 1;
|
||||
address = 0x8000;
|
||||
|
||||
while(1)
|
||||
{
|
||||
v = test_l2_address_alias(address, 0, 0x55555555, 0x55555555);
|
||||
if (v < 0)
|
||||
return -1;
|
||||
else if (v == 0)
|
||||
break;
|
||||
|
||||
size <<= 1;
|
||||
address <<= 1;
|
||||
|
||||
if (address > 0x200000)
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Mask size */
|
||||
size &= 0x3e;
|
||||
|
||||
/* Shift to [17:13] */
|
||||
size <<= 12;
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* Mask out the cache_setting */
|
||||
eax &= 0xfffc1fff;
|
||||
|
||||
/* Or in the calculated value */
|
||||
eax |= size;
|
||||
|
||||
/* Write cache size into BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
DBG("L2 Cache Mask is %x\n", size);
|
||||
|
||||
/* Shift to [6:2] */
|
||||
size >>= 11;
|
||||
|
||||
v = read_l2(2);
|
||||
|
||||
DBG("read_l2(2) = %x\n", v);
|
||||
|
||||
if (v < 0)
|
||||
return -1;
|
||||
|
||||
v &= 0x3;
|
||||
|
||||
/* Shift size right by v */
|
||||
size >>= v;
|
||||
|
||||
/* Or in this size */
|
||||
v |= size;
|
||||
|
||||
DBG("write_l2(2) = %x\n", v);
|
||||
|
||||
if (write_l2(2, v) != 0)
|
||||
return -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
int a, b, c;
|
||||
|
||||
a = read_l2(2);
|
||||
|
||||
DBG("read_l2(2) = %x\n", a);
|
||||
|
||||
if (a < 0)
|
||||
return -1;
|
||||
|
||||
b = a & 0x7;
|
||||
c = a >> 6;
|
||||
|
||||
a = 1<<c * b;
|
||||
|
||||
a &= 0xf;
|
||||
|
||||
DBG("Calculated a = %x\n", a);
|
||||
|
||||
if (a == 0)
|
||||
return -1;
|
||||
|
||||
/* Shift to 17:14 */
|
||||
a <<= 14;
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* Mask out the cache */
|
||||
eax &= 0xfffc1fff;
|
||||
|
||||
/* Or in the calculated value */
|
||||
eax |= a;
|
||||
|
||||
/* Write cache size into BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int calculate_l2_physical_address_range(void)
|
||||
{
|
||||
unsigned int eax, edx;
|
||||
int r0, r3;
|
||||
|
||||
r3 = read_l2(3);
|
||||
if (r3 < 0)
|
||||
return -1;
|
||||
|
||||
r0 = read_l2(0);
|
||||
if (r0 < 0)
|
||||
return -1;
|
||||
|
||||
if (r0 & 0x20)
|
||||
r3 = 0x7;
|
||||
else
|
||||
r3 &= 0x7;
|
||||
|
||||
DBG("L2 Physical Address Range is %dM\n", (1<<r3)*512);
|
||||
|
||||
/* Shift into [22:20] */
|
||||
r3 = r3 << 20;
|
||||
|
||||
/* Read BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
|
||||
/* Mask out [22:20] */
|
||||
eax &= 0xff8fffff;
|
||||
|
||||
/* Or in the new value */
|
||||
eax |= r3;
|
||||
|
||||
/* Write BBL_CR_CTL3 */
|
||||
wrmsr(0x11e, eax, edx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int calculate_l2_ecc(void)
|
||||
{
|
||||
unsigned int eax, edx;
|
||||
const unsigned int data1 = 0xaa55aa55;
|
||||
const unsigned int data2 = 0xaaaaaaaa;
|
||||
|
||||
/* Set User Supplied ECC in BBL_CR_CTL */
|
||||
rdmsr(0x119, eax, edx);
|
||||
eax |= 0x40000;
|
||||
wrmsr(0x119, eax, edx);
|
||||
|
||||
/* Write a value into the L2 Data ECC register BBL_CR_DECC */
|
||||
wrmsr(0x118, data1, 0);
|
||||
|
||||
if (test_l2_address_alias(0, 0, data2, data2) < 0)
|
||||
return -1;
|
||||
|
||||
/* Read back ECC from BBL_CR_DECC */
|
||||
rdmsr(0x118, eax, edx);
|
||||
|
||||
if (eax == data1)
|
||||
{
|
||||
DBG("L2 ECC Checking is enabled\n");
|
||||
|
||||
/* Set ECC Check Enable in BBL_CR_CTL3 */
|
||||
rdmsr(0x11e, eax, edx);
|
||||
eax |= 0x20;
|
||||
wrmsr(0x11e, eax, edx);
|
||||
}
|
||||
|
||||
/* Clear User Supplied ECC in BBL_CR_CTL */
|
||||
rdmsr(0x119, eax, edx);
|
||||
eax &= 0xfffbffff;
|
||||
wrmsr(0x119, eax, edx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,4 +1,29 @@
|
|||
#include <pci.h>
|
||||
|
||||
unsigned long sizeram()
|
||||
{
|
||||
return 0;
|
||||
unsigned long totalmem;
|
||||
unsigned char bank, mem, prevmem;
|
||||
// fix me later -- there are two more banks at 0x56 and 0x57
|
||||
unsigned long firstbank = 0x5a, lastbank = 0x5f;
|
||||
|
||||
struct pci_dev *pcidev;
|
||||
|
||||
pcidev = pci_find_slot(0, PCI_DEVFN(0,0));
|
||||
|
||||
if (! pcidev)
|
||||
return 0;
|
||||
|
||||
for(totalmem = mem = prevmem = 0, bank = firstbank;
|
||||
bank <= lastbank; bank++) {
|
||||
pci_read_config_byte(pcidev, bank, &mem);
|
||||
totalmem += (mem - prevmem) * 8 * 1024;
|
||||
prevmem = mem;
|
||||
}
|
||||
|
||||
printk("sizeram: NOT returning 0x%x KB\n", totalmem);
|
||||
printk("sizeram: there are still some SPD problems ... \n");
|
||||
totalmem = 64 * 1024;
|
||||
printk("sizeram: SO we return only 0x%x KB\n", totalmem);
|
||||
return totalmem;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue