From ab48be616ed21b3b5ca3085335fa49fa775f972d Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 24 Mar 2015 16:54:38 -0700 Subject: [PATCH] veyron: Increase SPI flash frequency to 24.75MHz This patch increases the SPI clock for the ROM to 24.75MHz on all Rk3288 (veyron) boards. This increases flash read speeds (and thereby decreases boot time) significantly, but we don't seem to get any more increases by going even higher. We have also seen occasional read failures at higher speeds in certain configurations, so this frequency seems to be the best option. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Booted on Jerry with Servo attached. Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720 Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/262645 Reviewed-by: David Hendricks (cherry picked from commit a1d07da4266f2922b076dfae8396c24c6a84252b) jwerner: Added Gus, Jaq and Minnie, removed Danger and Rialto. Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/262806 --- src/mainboard/google/veyron_brain/bootblock.c | 2 +- src/mainboard/google/veyron_gus/bootblock.c | 2 +- src/mainboard/google/veyron_jaq/bootblock.c | 2 +- src/mainboard/google/veyron_jerry/bootblock.c | 2 +- src/mainboard/google/veyron_mighty/bootblock.c | 2 +- src/mainboard/google/veyron_minnie/bootblock.c | 2 +- src/mainboard/google/veyron_pinky/bootblock.c | 2 +- src/mainboard/google/veyron_speedy/bootblock.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index ffa4bdecf8..1169455871 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -70,7 +70,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/veyron_gus/bootblock.c b/src/mainboard/google/veyron_gus/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_gus/bootblock.c +++ b/src/mainboard/google/veyron_gus/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_jaq/bootblock.c b/src/mainboard/google/veyron_jaq/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_jaq/bootblock.c +++ b/src/mainboard/google/veyron_jaq/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_jerry/bootblock.c +++ b/src/mainboard/google/veyron_jerry/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_mighty/bootblock.c +++ b/src/mainboard/google/veyron_mighty/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_minnie/bootblock.c b/src/mainboard/google/veyron_minnie/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_minnie/bootblock.c +++ b/src/mainboard/google/veyron_minnie/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c index cbb55ea4d2..1bc8840ade 100644 --- a/src/mainboard/google/veyron_speedy/bootblock.c +++ b/src/mainboard/google/veyron_speedy/bootblock.c @@ -68,7 +68,7 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);