aarch64/foundation-armv8: Set up RAM area and enter ramstage

Increase available RAM to 16M, register a ram_resource to it
and enter ramstage. Bounce buffer seems to be broken yet,
so assign the payload entry to be above coreboot area at
0x80000000 and it should jump to it.

BUG=None
BRANCH=none
TEST=Boot to minimal payload at 0x80100000 which halts the emulation

Change-Id: I77d6c56f5d4104c95283598b3d6ddabb8e5d0c7b
Signed-off-by: Marcelo Povoa <marcelogp@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186745
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Marcelo Povoa 2014-02-21 14:00:53 -08:00 committed by chrome-internal-fetch
commit ab3ecaff41
4 changed files with 7 additions and 4 deletions

View file

@ -186,7 +186,7 @@ ramstage-y += cbmem.c
$(obj)/arch/aarch64/coreboot_table.ramstage.o : $(OPTION_TABLE_H)
romstage-srcs += $(objgenerated)/crt0.s
#ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
ifeq ($(CONFIG_BOARD_HAS_HARD_RESET),y)
#ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c

View file

@ -111,10 +111,9 @@ config RAMBASE
hex
default SYS_SDRAM_BASE
# according to stefan, this is RAMBASE + 1M.
config RAMTOP
hex
default 0x80100000
default 0x81000000
config STACK_TOP
hex

View file

@ -19,9 +19,13 @@
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Enable foundation/armv8 device...\n");
ram_resource(dev, 0, CONFIG_RAMBASE / KiB,
(CONFIG_RAMTOP - CONFIG_RAMBASE) / KiB);
}
struct chip_operations mainboard_ops = {
CHIP_NAME("Foundation ARMv8 Model")
.enable_dev = mainboard_enable,
};

View file

@ -25,5 +25,5 @@ void main(void)
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
//stage_exit(entry);
stage_exit(entry);
}