From aaddb83491a26f3f6e193d0a287e272485f0b3f7 Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Sat, 28 Feb 2026 00:11:52 +0530 Subject: [PATCH] soc/intel/pantherlake: Configure TDC IRMS mode for WCL IA domain Set IA voltage regulator to use IRMS mode with 28 second time window for more accurate thermal design current measurement. Ref=:830097_WCL_PDG_SchChk_Rev1p5 BUG=b:None TEST=Build ocelot and verify that the system boots with the following VR parameter [SPEW ] TdcMode[0]:0x1 [SPEW ] TdcMode[1]:0x0 [SPEW ] TdcMode[2]:0x0 [SPEW ] TdcMode[3]:0x0 [SPEW ] TdcTimeWindow[0]:0x6D60 [SPEW ] TdcTimeWindow[1]:0x0 [SPEW ] TdcTimeWindow[2]:0x0 [SPEW ] TdcTimeWindow[3]:0x0 Change-Id: I4b7b9484d47cf9d98548cfc8b53e47be4e21c4d1 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/91455 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chipset_wcl.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/pantherlake/chipset_wcl.cb b/src/soc/intel/pantherlake/chipset_wcl.cb index 4d8d296aa5..ed32d4826d 100644 --- a/src/soc/intel/pantherlake/chipset_wcl.cb +++ b/src/soc/intel/pantherlake/chipset_wcl.cb @@ -12,6 +12,9 @@ chip soc/intel/pantherlake [VR_DOMAIN_GT] = 36 * 4, }" + register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS" + register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000" + # Reduce the size of BasicMemoryTests to speed up the boot time. register "lower_basic_mem_test_size" = "true"