erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/nissa/var/yavilla: Generate SPD ID to aligen with yaviks

Browse source 
Yavilla board memory id setting references to yaviks.
This CL aligen it with yaviks.

    DRAM Part Name                 ID to assign
    MT62F512M32D2DR-031 WT:B       0 (0000)
    MT62F1G32D4DR-031 WT:B         1 (0001)
    H9JCNNNBK3MLYR-N6E             0 (0000)
    H58G56AK6BX069                 2 (0010)
    K3LKBKB0BM-MGCP                2 (0010)
    H58G56BK7BX068                 3 (0011)
    MT62F1G32D2DS-026 WT:B         3 (0011)
    K3KL8L80CM-MGCT                3 (0011)
    H58G66BK7BX067                 4 (0100)
    MT62F2G32D4DS-026 WT:B         4 (0100)
    K3KL9L90CM-MGCT                4 (0100)
    H58G66AK6BX070                 5 (0101)

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=run part_id_gen to generate SPD id

Change-Id: I4a5eb9e6e87a4adbc23f94f0eb92d5452c50e47c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Tony Huang 2023-04-20 15:03:35 +08:00 • committed by Felix Held
commit aad8824741
3 changed files with 19 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/mainboard/google/brya/variants/yavilla/memory/Makefile.inc
View file

@ -5,5 +5,8 @@
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = H58G56BK7BX068, MT62F1G32D2DS-026 WT:B, K3KL8L80CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 4(0b0100) Parts = H58G66BK7BX067, MT62F2G32D4DS-026 WT:B, K3KL9L90CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 5(0b0101) Parts = H58G66AK6BX070

16
src/mainboard/google/brya/variants/yavilla/memory/dram_id.generated.txt
View file

@ -5,10 +5,14 @@
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56BK7BX068 1 (0001)
MT62F1G32D2DS-026 WT:B 1 (0001)
K3KL8L80CM-MGCT 1 (0001)
H58G66BK7BX067 2 (0010)
MT62F2G32D4DS-026 WT:B 2 (0010)
K3KL9L90CM-MGCT 2 (0010)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
H58G56BK7BX068 3 (0011)
MT62F1G32D2DS-026 WT:B 3 (0011)
K3KL8L80CM-MGCT 3 (0011)
H58G66BK7BX067 4 (0100)
MT62F2G32D4DS-026 WT:B 4 (0100)
K3KL9L90CM-MGCT 4 (0100)
H58G66AK6BX070 5 (0101)

4
src/mainboard/google/brya/variants/yavilla/memory/mem_parts_used.txt
View file

@ -10,10 +10,14 @@
# Part Name
MT62F512M32D2DR-031 WT:B
MT62F1G32D4DR-031 WT:B
H9JCNNNBK3MLYR-N6E
H58G56AK6BX069
K3LKBKB0BM-MGCP
H58G56BK7BX068
MT62F1G32D2DS-026 WT:B
K3KL8L80CM-MGCT
H58G66BK7BX067
MT62F2G32D4DS-026 WT:B
K3KL9L90CM-MGCT
H58G66AK6BX070