From aad63ddd8a1dfe59786697209b48ba39fa336af7 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Fri, 22 Aug 2008 19:42:45 +0000 Subject: [PATCH] Improve comments in Fam10h CAR. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://coreboot.org/repository/coreboot-v3@806 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/amd/stage0.S | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/x86/amd/stage0.S b/arch/x86/amd/stage0.S index 8a87eb8e22..f6d50965e1 100644 --- a/arch/x86/amd/stage0.S +++ b/arch/x86/amd/stage0.S @@ -180,10 +180,10 @@ cache_as_ram_setup: /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */ /* Only BSP needed, for other nodes set during HT/memory init. */ - /* So we need to check if it is BSP */ - movl $0x1b, %ecx + /* So we need to check if it is BSP/BSC */ + movl $0x1b, %ecx /* APIC Base Address Register */ rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC Boot Strap CPU Core */ jnc CAR_FAM10_out /* Enable RT tables on BSP */ @@ -341,10 +341,10 @@ clear_fixed_var_mtrr_out: #ifdef CONFIG_CPU_AMD_K10 - /* So we need to check if it is BSP */ - movl $0x1b, %ecx + /* So we need to check if it is BSP/BSC */ + movl $0x1b, %ecx /* APIC BAR */ rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC */ jnc CAR_FAM10_ap #endif