diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
index 9b21d381e0..b549276b35 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/devicetree.cb
@@ -118,10 +118,8 @@ chip soc/intel/elkhartlake
 	register "PchTsnGbeLinkSpeed" = "Tsn_1_Gbps"
 	register "PchTsnGbeSgmiiEnable" = "1"
 	register "PseDmaOwn[0]" = "Host_Owned"
-	register "PseDmaOwn[1]" = "Host_Owned"
 	register "pch_tsn_phy_irq_edge" = "RISING_EDGE"
 	register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE"
-	register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE"
 
 
 	# FIVR related settings
@@ -221,25 +219,6 @@ chip soc/intel/elkhartlake
 				end
 			end
 		end
-		device pci 1d.2 on	    # Intel PSE Time-Sensitive Networking GbE 1
-			# Enable external Marvell PHY 88E1512
-			chip drivers/net/phy/m88e1512
-				register "configure_leds" = "true"
-				# LED[0]: On - 1000 Mbps Link, Off - Else
-				register "led_0_ctrl" = "7"
-				# LED[1]: On - Link, Blink - Activity, Off - No Link
-				register "led_1_ctrl" = "1"
-				# INTn is routed to LED[2] pin
-				register "enable_int" = "true"
-				register "downshift_cnt" = "2"
-				register "force_mos" = "true"
-				register "pmos_val" = "0xF"
-				register "nmos_val" = "0xA"
-				device mdio 1 on    # PHY address
-					ops m88e1512_ops
-				end
-			end
-		end
 
 		device pci 1e.0 on	end # UART0
 		device pci 1e.1 on	end # UART1
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
index 7e68cf9a6b..f23ac25ce3 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl6/gpio.c
@@ -46,10 +46,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),		/* EMMC_RESET */
 
 	/* Community 1 - GpioGroup GPP_H */
-	PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1),		/* PSE_GBE1_INT */
-	PAD_CFG_GPO(GPP_H1, 1, DEEP),			/* PSE_GBE1_RST_N */
-	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1),		/* PSE_GBE1_AUXTS */
-	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),		/* PSE_GBE1_PPS */
 	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),		/* PCIE_CLKREQ4_N */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),		/* PCIE_CLKREQ5_N */
 
@@ -89,25 +85,11 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD2 */
 	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD1 */
 	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXD0 */
-	PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD3 */
-	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD2 */
-	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD1 */
-	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXD0 */
-	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCLK */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_TXCTL */
-	PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCLK */
-	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXCTL */
-	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD3 */
-	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD2 */
-	PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD1 */
-	PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),		/* PSE_GBE1_RGMII_RXD0 */
 	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),		/* PSE_GBE0_RGMII_RXCTL */
 
 	/* Community 4 - GpioGroup GPP_C */
 	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),		/* PSE_GBE0_MDC */
 	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),		/* PSE_GBE0_MDIO */
-	PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),		/* PSE_GBE1_MDC */
-	PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),		/* PSE_GBE1_MDIO */
 	PAD_NC(GPP_C8, NONE),				/* Not connected */
 	PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4),		/* SIO_UART1_RXD */
 	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4),		/* SIO_UART1_TXD */