diff --git a/src/mainboard/google/fatcat/variants/moonstone/gpio.c b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
index 7f6aa0cdb7..eb1db7839a 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/gpio.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/gpio.c
@@ -195,7 +195,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
 	/* GPP_E05:     TCHSCR_RPT_EN */
-	PAD_CFG_GPO(GPP_E05, 0, PLTRST),
+	PAD_CFG_GPO(GPP_E05, 1, PLTRST),
 	/* GPP_E06:     NC */
 	PAD_NC(GPP_E06, NONE),
 	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
@@ -256,7 +256,7 @@ static const struct pad_config gpio_table[] = {
 	/* GPP_F13:     TCHSCR_I2C5_SDA */
 	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
 	/* GPP_F16:     TCHSCR_RST_L */
-	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
 	/* GPP_F17:     NC */
 	PAD_NC(GPP_F17, NONE),
 	/* GPP_F18:     TCHSCR_INT_L */
@@ -392,6 +392,8 @@ static const struct pad_config romstage_gpio_table[] = {
 	PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
 	/* GPP_E03:     GEN5_SSD_RESET_N */
 	PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+	/* GPP_F08:     EN_TCHSCR_PWR */
+	PAD_CFG_GPO(GPP_F08, 1, DEEP),
 };
 
 const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
index cced66807a..277aca3050 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
+++ b/src/mainboard/google/fatcat/variants/moonstone/include/variant/gpio.h
@@ -8,4 +8,6 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK
 
+#define TCHSCR_RST_L	GPP_F16
+
 #endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
index 28b2fec984..f714b4eafa 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
@@ -473,10 +473,8 @@ chip soc/intel/pantherlake
 				register "generic.desc" = ""Focal Touchscreen""
 				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
 				register "generic.detect" = "1"
-				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)"
-				register "generic.reset_delay_ms" = "20"
-				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)"
-				register "generic.enable_delay_ms" = "6"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E05)"
+				register "generic.stop_off_delay_ms" = "1"
 				register "generic.has_power_resource" = "1"
 				register "generic.use_gpio_for_status" = "true"
 				register "hid_desc_reg_offset" = "0x01"
diff --git a/src/mainboard/google/fatcat/variants/moonstone/variant.c b/src/mainboard/google/fatcat/variants/moonstone/variant.c
index 17ce4d2c2f..4af4421449 100644
--- a/src/mainboard/google/fatcat/variants/moonstone/variant.c
+++ b/src/mainboard/google/fatcat/variants/moonstone/variant.c
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <fw_config.h>
 #include <sar.h>
+#include <variant/gpio.h>
 
 const char *get_wifi_sar_cbfs_filename(void)
 {
@@ -66,3 +67,11 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 		config->tcss_ports[3] = (struct tcss_port_config) TCSS_PORT_DEFAULT(OC_SKIP);
 	}
 }
+
+void fw_config_post_gpio_configure(void)
+{
+	/* ensures touchscreen reset pin is asserted at the correct stage,
+	   satisfying the requirement that reset must occur after BL_ON. */
+	gpio_output(TCHSCR_RST_L, 1);
+	printk(BIOS_INFO, "TSR: assert touchscreen reset pin ...\n");
+}