From aa1d44b6446018fabe3cf8eac6662aaea4a1996c Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Mon, 17 Nov 2025 15:33:16 +0800 Subject: [PATCH] mb/google/ocelot/var/kodkod: Update gpio settings Configure GPIOs according to schematics_20251112. BUG=b:452542491 TEST=emerge-ocelot coreboot Change-Id: I74890f5980d392fbee75559299fb56fca8ca996a Signed-off-by: Ian Feng Reviewed-on: https://review.coreboot.org/c/coreboot/+/90068 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- .../google/ocelot/variants/kodkod/gpio.c | 345 ++++++++++-------- 1 file changed, 189 insertions(+), 156 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/kodkod/gpio.c b/src/mainboard/google/ocelot/variants/kodkod/gpio.c index 8c9686ea2d..e8884d9c43 100644 --- a/src/mainboard/google/ocelot/variants/kodkod/gpio.c +++ b/src/mainboard/google/ocelot/variants/kodkod/gpio.c @@ -29,114 +29,128 @@ static const struct pad_config gpio_table[] = { /* GPP_A06: ESPI_RST_AIC_N */ /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ - /* GPP_A08: M2_GEN4_SSD_RESET_N */ + /* GPP_A08: SOC_SSD_RST# */ PAD_CFG_GPO(GPP_A08, 1, PLTRST), /* GPP_A09: NC */ PAD_NC(GPP_A09, NONE), /* GPP_A10: NC */ PAD_NC(GPP_A10, NONE), - /* GPP_A11: NC */ + /* GPP_A11: SOC_WLAN_RST# */ PAD_NC(GPP_A11, NONE), - /* GPP_A12: NC */ + /* GPP_A12: NC*/ PAD_NC(GPP_A12, NONE), - /* GPP_A13: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC_DRIVER(GPP_A13, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_A13: NC */ + PAD_NC(GPP_A13, NONE), /* GPP_A15: NC */ PAD_NC(GPP_A15, NONE), /* GPP_B */ - /* GPP_B00: USBC_SML_CLK_PD */ + /* GPP_B00: SOC_USBC_SMLCLK */ PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), - /* GPP_B01: USBC_SML_DATA_PD */ + /* GPP_B01: SOC_USBC_SMLDATA */ PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), - /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */ + /* GPP_B02: NC */ PAD_NC(GPP_B02, NONE), - /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */ + /* GPP_B03: NC */ PAD_NC(GPP_B03, NONE), - /* GPP_B04: ISH_GP_0_SNSR_HDR */ + /* GPP_B04: NC */ PAD_NC(GPP_B04, NONE), - /* GPP_B06: SOC_PDB_CTRL */ - PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B05: NC */ + PAD_NC(GPP_B05, NONE), + /* GPP_B06: NC */ + PAD_NC(GPP_B06, NONE), + /* GPP_B07: NC */ + PAD_NC(GPP_B07, NONE), /* GPP_B08: NC */ PAD_NC(GPP_B08, NONE), - /* GPP_B09: BT_RF_KILL_N */ - PAD_CFG_GPO(GPP_B09, 1, DEEP), + /* GPP_B09: NC */ + PAD_NC(GPP_B09, NONE), /* GPP_B10: NC */ PAD_NC(GPP_B10, NONE), - /* GPP_B12: PM_SLP_S0_N */ + /* GPP_B12: PM_SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - /* GPP_B13: PLT_RST_N */ + /* GPP_B13: SOC_PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - /* GPP_B14: GPP_B14_DDSP_HPDB */ + /* GPP_B14: SOC_DP2_HPD# */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), /* GPP_B16: NC */ PAD_NC(GPP_B16, NONE), - /* GPP_B17: SPI_TPM_INT_N */ + /* GPP_B17: SOC_SPI_TPM_INT# */ PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG), - /* GPP_B20: SOC_KB_MATRIX */ - PAD_CFG_GPO(GPP_B20, 1, PLTRST), - /* GPP_B21: TCP_RETIMER_FORCE_PWR */ - PAD_CFG_GPO(GPP_B21, 0, DEEP), - /* GPP_B22: SOC_CAM_WP */ - PAD_CFG_GPO(GPP_B22, 0, DEEP), - /* GPP_B24: ESPI_ALERT0_EC_R_N */ + /* GPP_B18: NC */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19: NC */ + PAD_NC(GPP_B19, NONE), + /* GPP_B20: NC */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21: NC */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22: NC */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23: NC */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24: NC */ PAD_NC(GPP_B24, NONE), - /* GPP_B25: None */ + /* GPP_B25: NC */ PAD_NC(GPP_B25, NONE), /* GPP_C */ - /* GPP_C00: SPD_SMB_CLK */ + /* GPP_C00: SPD_SOC_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: SPD_SMB_DATA */ + /* GPP_C01: SPD_SOC_SMBDATA */ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_C02: NC */ PAD_NC(GPP_C02, NONE), - /* GPP_C03: TCP_LAN_SML0_SCL_R */ - PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), - /* GPP_C04: TCP_LAN_SML0_SDA_R */ - PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C03: NC */ + PAD_NC(GPP_C03, NONE), + /* GPP_C04: NC */ + PAD_NC(GPP_C04, NONE), /* GPP_C05: NC */ PAD_NC(GPP_C05, NONE), /* GPP_C06: NC */ PAD_NC(GPP_C06, NONE), /* GPP_C07: NC */ PAD_NC(GPP_C07, NONE), - /* GPP_C08: PM_SLP_S0_N_GPP_CNTRL */ + /* GPP_C08: PM_SLP_S0#_GATE */ PAD_CFG_GPO(GPP_C08, 1, PLTRST), - /* GPP_C09: NC */ - PAD_NC(GPP_C09, NONE), - /* GPP_C10: WIFI_RF_KILL_N */ + /* GPP_C09: CLKREQ_PCIE#0_WLAN */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C10: SOC_WIFI_KILL# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* GPP_C11: NC */ - PAD_NC(GPP_C11, NONE), - /* GPP_C12: CLKREQ3_X4_GEN4_M2_SSD_N */ + /* GPP_C11: CLKREQ_PCIE#2_LAN */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: CLKREQ_PCIE#3_SSD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* GPP_C13: NC */ PAD_NC(GPP_C13, NONE), /* GPP_C14: NC */ PAD_NC(GPP_C14, NONE), - /* GPP_C15: FPS_RST_N */ + /* GPP_C15: SOC_FPS_RST# */ PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), - /* GPP_C16: MOD_TCSS1_LS_TX_DDC_SCL */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* GPP_C17: MOD_TCSS1_LS_RX_DDC_SDA */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* GPP_C18: MOD_TCSS2_LS_TX_DDC_SCL */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* GPP_C19: MOD_TCSS2_LS_RX_DDC_SDA */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* GPP_C22: DDPB_HDMI_CTRLCLK */ + /* GPP_C16: NC */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17: NC */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18: NC */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19: NC */ + PAD_NC(GPP_C19, NONE), + /* GPP_C22: SOC_DP2_CTRL_CLK */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2), - /* GPP_C23: DDPB_HDMI_CTRLDATA */ + /* GPP_C23: SOC_DP2_CTRL_DATA */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2), /* GPP_D */ /* GPP_D01: NC */ PAD_NC(GPP_D01, NONE), - /* GPP_D02: SOC_WP_OD */ - PAD_CFG_GPO(GPP_D02, 0, DEEP), + /* GPP_D02: SOC_SPI_WP_H1 */ + PAD_CFG_GPI(GPP_D02, NONE, DEEP), /* GPP_D03: NC */ PAD_NC(GPP_D03, NONE), + /* GPP_D05: NC */ + PAD_NC(GPP_D05, NONE), + /* GPP_D06: NC */ + PAD_NC(GPP_D06, NONE), /* GPP_D07: NC */ PAD_NC(GPP_D07, NONE), /* GPP_D08: NC */ @@ -147,151 +161,153 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D10, NONE), /* GPP_D11: NC */ PAD_NC(GPP_D11, NONE), - /* GPP_D12: NONE */ + /* GPP_D12: NC */ PAD_NC(GPP_D12, NONE), /* GPP_D13: NC */ PAD_NC(GPP_D13, NONE), - /* GPP_D16: NC */ - PAD_NC(GPP_D16, NONE), - /* GPP_D17: NC */ - PAD_NC(GPP_D17, NONE), + /* GPP_D16: SOC_DMIC_CLK1 */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF3), + /* GPP_D17: SOC_DMIC_DATA1 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF3), /* GPP_D19: NC */ PAD_NC(GPP_D19, NONE), - /* GPP_D21: GPP_D21_UFS_REFCLK_R */ - PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* GPP_D21: NC */ + PAD_NC(GPP_D21, NONE), /* GPP_E */ - /* GPP_E01: PM_SLP_DRAM_N */ - PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2), + /* GPP_E01: NC */ + PAD_NC(GPP_E01, NONE), /* GPP_E02: VR_ALERT#_R */ - PAD_NC(GPP_E02, NONE), + PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2), /* GPP_E03: NC */ PAD_NC(GPP_E03, NONE), /* GPP_E05: NC */ PAD_NC(GPP_E05, NONE), - /* GPP_E06: CAM_PRIVACY */ - PAD_CFG_GPO(GPP_E06, 1, DEEP), + /* GPP_E06: NC */ + PAD_NC(GPP_E06, NONE), /* GPP_E07: NC */ PAD_NC(GPP_E07, NONE), - /* GPP_E08: NC */ - PAD_NC(GPP_E08, NONE), - /* GPP_E09: USB_FP_CONN_1_CONN_2_OC0_N */ + /* GPP_E08: SOC_BT_KILL# */ + PAD_CFG_GPO(GPP_E08, 1, DEEP), + /* GPP_E09: SOC_USB_OC0# */ PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), - /* GPP_E10: NONE */ + /* GPP_E10: NC */ PAD_NC(GPP_E10, NONE), /* GPP_E11: NC */ PAD_NC(GPP_E11, NONE), - /* GPP_E12: THC_I2C0_SCL_TCH_PNL1 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), - /* GPP_E13: THC_I2C0_SDA_TCH_PNL1 */ - PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E12: SOC_THC_I2C_0_SCL */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13: SOC_THC_I2C_0_SDA */ + PAD_NC(GPP_E13, NONE), /* GPP_E14: NC */ PAD_NC(GPP_E14, NONE), /* GPP_E15: NC */ PAD_NC(GPP_E15, NONE), - /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + /* GPP_E16: SOC_TCHSCR_RST# */ + PAD_NC(GPP_E16, NONE), /* GPP_E17: NC */ PAD_NC(GPP_E17, NONE), - /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: FPS_INT_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E19, NONE, PWROK, LEVEL, INVERT), - /* GPP_E20: FPS_FW_UPDATE */ - PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), - /* GPP_E21: I2C_PMC_PD_INT_N */ + /* GPP_E18: SOC_TCHSCR_INT# */ + PAD_NC(GPP_E18, NONE), + /* GPP_E19: SOC_WL_WAKE# */ + PAD_NC(GPP_E19, NONE), + /* GPP_E20: SOC_TP_INT# */ + PAD_CFG_GPI_APIC_DRIVER(GPP_E20, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_E21: SOC_I2C_PD_INT# */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22: NC */ PAD_NC(GPP_E22, NONE), /* GPP_F */ - /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + /* GPP_F00: CNV_BRI_CTX_DRX */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), - /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* GPP_F01: CNV_BRI_CRX_DTX */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), - /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* GPP_F02: CNV_RGI_CTX_DRX */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), - /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* GPP_F03: CNV_RGI_CRX_DTX */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), - /* GPP_F04: CNV_RF_RESET_R_N */ + /* GPP_F04: CNV_RF_RESET# */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), - /* GPP_F05: CRF_CLKREQ_R */ + /* GPP_F05: CLKREQ_CNV# */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), /* GPP_F06: NC */ PAD_NC(GPP_F06, NONE), /* GPP_F07: NC */ PAD_NC(GPP_F07, NONE), - /* GPP_F08: TCH_PNL1_PWR_EN */ - PAD_CFG_GPO(GPP_F08, 1, PLTRST), - /* GPP_F09: M2_UFS_RST_N */ - PAD_CFG_GPO(GPP_F09, 1, DEEP), - /* GPP_F10: SOC_EC_INT */ + /* GPP_F08: SOC_TCH_PWR_EN */ + PAD_NC(GPP_F08, NONE), + /* GPP_F09: NC */ + PAD_NC(GPP_F09, NONE), + /* GPP_F10: EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST, LEVEL, INVERT), /* GPP_F11: NC */ PAD_NC(GPP_F11, NONE), - /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), - /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_F14: GPP_F14_GPSI0A_MOSI */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), - /* GPP_F15: GPP_F15_GSPI0A_MISO */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), - /* GPP_F16: GPP_F16_GSPI0A_CLK */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F12: NC */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13: NC */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14: NC */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15: NC */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16: NC */ + PAD_NC(GPP_F16, NONE), /* GPP_F17: NC */ PAD_NC(GPP_F17, NONE), - /* GPP_F18: GPP_F18_GSPI0A_CS0 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), + /* GPP_F18: NC */ + PAD_NC(GPP_F18, NONE), /* GPP_F19: NC */ PAD_NC(GPP_F19, NONE), /* GPP_F20: CSE_EARLY_SW */ PAD_CFG_GPI(GPP_F20, NONE, DEEP), - /* GPP_F22: THC1_SPI2_DSYNC */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: NC */ + PAD_NC(GPP_F23, NONE), /* GPP_H */ /* GPP_H00: NC */ PAD_NC(GPP_H00, NONE), - /* GPP_H01: M2_UFS_SLP_N */ - PAD_CFG_GPO(GPP_H01, 1, DEEP), - /* GPP_H02: DEBUG_TRACE_PNP */ - PAD_CFG_GPO(GPP_H02, 1, PLTRST), - /* GPP_H03: MIC MUTE */ - PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1), + /* GPP_H01: NC */ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: NC */ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: NC */ + PAD_NC(GPP_H03, NONE), /* GPP_H04: NC */ PAD_NC(GPP_H04, NONE), /* GPP_H05: NC */ PAD_NC(GPP_H05, NONE), - /* GPP_H06: I2C3_SCL_AUDIO_HDR */ + /* GPP_H06: SOC_I2C_3_SDA_iPCM */ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SDA_AUDIO_HDR */ + /* GPP_H07: SOC_I2C_3_SCL_iPCM */ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), - /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ + /* GPP_H08: UART_0_CRXD_DTXD */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ + /* GPP_H09: UART_0_CTXD_DRXD */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* GPP_H10: NC */ PAD_NC(GPP_H10, NONE), /* GPP_H11: NC */ PAD_NC(GPP_H11, NONE), - /* GPP_H13: CPU_C10_GATE_N_R */ - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - /* GPP_H14: ISH_I3C1_SDA_SNSR_HDR */ + /* GPP_H13: NC */ + PAD_NC(GPP_H13, NONE), + /* GPP_H14: NC */ PAD_NC(GPP_H14, NONE), - /* GPP_H15: ISH_I3C1_SCL_SNSR_HDR */ + /* GPP_H15: NC */ PAD_NC(GPP_H15, NONE), - /* GPP_H17: MIC MUTE LED */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - /* GPP_H18: GEN4_SSD_PWREN */ - PAD_CFG_GPO(GPP_H18, 1, DEEP), - /* GPP_H19: I3C0_SDA_HDR */ - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2), - /* GPP_H20: I3C0_SCL_HDR */ - PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2), - /* GPP_H21: I2C1_SDA_TTK_CHROME */ + /* GPP_H17: NC */ + PAD_NC(GPP_H17, NONE), + /* GPP_H18: NC */ + PAD_NC(GPP_H18, NONE), + /* GPP_H19: SOC_I2C_0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20: SOC_I2C_0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21: SOC_I2C_1_SDA */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: I2C1_SCL_TTK_CHROME */ + /* GPP_H22: SOC_I2C_1_SCL */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* GPP_H23: NC */ PAD_NC(GPP_H23, NONE), @@ -299,65 +315,82 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H24, NONE), /* GPP_V */ - /* GPP_V00: PM_BATLOW_N */ + /* GPP_V00: BATLOW# */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), /* GPP_V01: BC_ACOK_MCP */ PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), - /* GPP_V02: LANWAKE_N_R */ + /* GPP_V02: WAKE# */ PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), - /* GPP_V03: PWRBTN_MCP_N */ + /* GPP_V03: EC_PWRBTN#_OUT_R */ PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), - /* GPP_V04: PM_SLP_S3_N */ + /* GPP_V04: PM_SLP_S3# */ PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), - /* GPP_V05: PM_SLP_S4_N */ + /* GPP_V05: PM_SLP_S4# */ PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), - /* GPP_V06: PM_SLP_A_N */ + /* GPP_V06: PM_SLP_A# */ PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), - /* GPP_V07: M.2_BTWIFI_SUS_CLK_LS */ + /* GPP_V07: WLAN_SUSCLK */ PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), - /* GPP_V08: SLP_WLAN_N */ - PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), - /* GPP_V09: PM_SLP_S5_N */ + /* GPP_V08: NC */ + PAD_NC(GPP_V08, NONE), + /* GPP_V09: PM_SLP_S5# */ PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), - /* GPP_V10: NC */ - PAD_NC(GPP_V10, NONE), - /* GPP_V11: PM_SLP_LAN_N */ + /* GPP_V10: LAN_WAKE# */ + PAD_CFG_GPI_IRQ_WAKE(GPP_V10, NONE, PWROK, LEVEL, INVERT), + /* GPP_V11: PM_SLP_LAN# */ PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), - /* GPP_V12: WAKE_N */ - PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V12: NC */ + PAD_NC(GPP_V12, NONE), /* GPP_V13: GPP_V13_CATERR_N */ PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), /* GPP_V14: GPP_V14_FORCEPR_N */ PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* GPP_V15: GPP_V15_THERMTRIP_N */ PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), - /* GPP_V16: GPP_V16_VCCST_EN */ + /* GPP_V16: SOC_VCCST_EN */ PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + + /* GPP_S00: SNDW_3_SCL */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW_3_SDA0 */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SNDW_3_SDA1 */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1), + /* GPP_S03: SNDW_3_SDA2 */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1), + /* GPP_S04: NC */ + PAD_NC(GPP_S04, NONE), + /* GPP_S05: NC */ + PAD_NC(GPP_S05, NONE), + /* GPP_S06: NC */ + PAD_NC(GPP_S06, NONE), + /* GPP_S07: NC */ + PAD_NC(GPP_S07, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* GPP_B17: SPI_TPM_INT_N */ - PAD_CFG_GPI_APIC(GPP_B17, NONE, DEEP, LEVEL, INVERT), - /* GPP_H06: I2C3_SDA_PSS */ + /* GPP_B17: SOC_SPI_TPM_INT# */ + PAD_CFG_GPI_APIC_LOCK(GPP_B17, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_H06: SOC_I2C_3_SDA_iPCM */ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), - /* GPP_H07: I2C3_SCL_PSS */ + /* GPP_H07: SOC_I2C_3_SCL_iPCM */ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), - /* GPP_H08: SOC_BIOS_LOG_TTK_UART_RX */ + /* GPP_H08: UART_0_CRXD_DTXD */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* GPP_H09: SOC_BIOS_LOG_TTK_UART_TX */ + /* GPP_H09: UART_0_CTXD_DRXD */ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), - /* GPP_H21: I2C1_SDA_TTK_CHROME */ + /* GPP_H21: SOC_I2C_1_SDA */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - /* GPP_H22: I2C1_SCL_TTK_CHROME */ + /* GPP_H22: SOC_I2C_1_SCL */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), }; /* Pad configuration in romstage */ static const struct pad_config romstage_gpio_table[] = { - /* GPP_C00: SPD_SMB_CLK */ + /* GPP_C00: SPD_SOC_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), - /* GPP_C01: SPD_SMB_DATA */ + /* GPP_C01: SPD_SOC_SMBDATA */ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_C15: FPS_RST_N */ PAD_CFG_GPO(GPP_C15, 0, PLTRST),