diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 9f0cdc5687..9b5474b021 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -9,6 +9,7 @@ if SOC_INTEL_BAYTRAIL
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select CACHE_MRC_SETTINGS
+	select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
 	select CACHE_ROM
 	select CAR_MIGRATION
 	select COLLECT_TIMESTAMPS
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 78174cc944..46532c1067 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -25,12 +25,16 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
+#include <ramstage_cache.h>
+#include <ramstage_cache.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include <baytrail/gpio.h>
 #include <baytrail/iomap.h>
 #include <baytrail/lpc.h>
 #include <baytrail/pci_devs.h>
+#include <baytrail/reset.h>
 #include <baytrail/romstage.h>
 
 /* The cache-as-ram assembly file calls romstage_main() after setting up
@@ -155,6 +159,9 @@ void asmlinkage romstage_after_car(void)
 
 	timestamp_add_now(TS_END_ROMSTAGE);
 
+	/* Run vboot verification if configured. */
+	vboot_verify_firmware(romstage_handoff_find_or_add());
+
 	/* Load the ramstage. */
 	copy_and_run();
 	while (1);
@@ -256,3 +263,25 @@ static void *setup_stack_and_mttrs(void)
 
 	return slot;
 }
+
+struct ramstage_cache *ramstage_cache_location(long *size)
+{
+	char *smm_base;
+	/* 1MiB cache size */
+	const long cache_size = (1 << 20);
+
+	/* Ramstage cache lives in TSEG region which is the definition of
+	 * cbmem_top(). */
+	smm_base = cbmem_top();
+	*size = cache_size;
+	return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size];
+}
+
+void ramstage_cache_invalid(struct ramstage_cache *cache)
+{
+#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+	/* Perform cold reset on invalid ramstage cache. */
+	cold_reset();
+#endif
+}
+