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UART 8250: Unconditionally provide register constants and use UART8250 prefix.

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The register indexes and bitfield masks were guarded by the UART8250 config
options, but it might be (is) necessary to use them in a driver that is
UART8250 like without actually using the 8250 driver itself. To avoid any name
collision with other drivers, also change the constant prefix from UART_ to
UART8250_.

BUG=None
TEST=Built for link, lumpy, pit, and nyan. With this and other changes, got
bootblock serial output on nyan.
BRANCH=None

Change-Id: Ie606d9e0329132961c3004688176204a829569dc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171336
Reviewed-by: Ronald Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
This commit is contained in:
Gabe Black 2013-09-30 21:25:49 -07:00 • committed by chrome-internal-fetch
commit a93900be8d
4 changed files with 111 additions and 113 deletions
Download patch file Download diff file Expand all files Collapse all files

24
src/lib/uart8250.c
View file

@ -40,7 +40,7 @@
static inline int uart8250_can_tx_byte(unsigned base_port)
{
return inb(base_port + UART_LSR) & UART_LSR_THRE;
return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE;
}
static inline void uart8250_wait_to_tx_byte(unsigned base_port)
@ -52,13 +52,13 @@ static inline void uart8250_wait_to_tx_byte(unsigned base_port)
static inline void uart8250_wait_until_sent(unsigned base_port)
{
unsigned long int i = FIFO_TIMEOUT;
while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
while (i-- && !(inb(base_port + UART8250_LSR) & UART8250_LSR_TEMT));
}
void uart8250_tx_byte(unsigned base_port, unsigned char data)
{
uart8250_wait_to_tx_byte(base_port);
outb(data, base_port + UART_TBR);
outb(data, base_port + UART8250_TBR);
}
void uart8250_tx_flush(unsigned base_port)
@ -68,7 +68,7 @@ void uart8250_tx_flush(unsigned base_port)
int uart8250_can_rx_byte(unsigned base_port)
{
return inb(base_port + UART_LSR) & UART_LSR_DR;
return inb(base_port + UART8250_LSR) & UART8250_LSR_DR;
}
unsigned char uart8250_rx_byte(unsigned base_port)
@ -77,7 +77,7 @@ unsigned char uart8250_rx_byte(unsigned base_port)
while (i-- && !uart8250_can_rx_byte(base_port));
if (i)
return inb(base_port + UART_RBR);
return inb(base_port + UART8250_RBR);
else
return 0x0;
}
@ -86,22 +86,22 @@ void uart8250_init(unsigned base_port, unsigned divisor)
{
DISABLE_TRACE;
/* Disable interrupts */
outb(0x0, base_port + UART_IER);
outb(0x0, base_port + UART8250_IER);
/* Enable FIFOs */
outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
outb(UART8250_FCR_FIFO_EN, base_port + UART8250_FCR);
/* assert DTR and RTS so the other end is happy */
outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
outb(UART8250_MCR_DTR | UART8250_MCR_RTS, base_port + UART8250_MCR);
/* DLAB on */
outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
outb(UART8250_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
/* Set Baud Rate Divisor. 12 ==> 9600 Baud */
outb(divisor & 0xFF, base_port + UART_DLL);
outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
outb(divisor & 0xFF, base_port + UART8250_DLL);
outb((divisor >> 8) & 0xFF, base_port + UART8250_DLM);
/* Set to 3 for 8N1 */
outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
ENABLE_TRACE;
}

24
src/lib/uart8250mem.c
View file

@ -40,7 +40,7 @@
static inline int uart8250_mem_can_tx_byte(unsigned base_port)
{
return read8(base_port + UART_LSR) & UART_LSR_THRE;
return read8(base_port + UART8250_LSR) & UART8250_LSR_THRE;
}
static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port)
@ -53,14 +53,14 @@ static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port)
static inline void uart8250_mem_wait_until_sent(unsigned base_port)
{
unsigned long int i = FIFO_TIMEOUT;
while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
while(i-- && !(read8(base_port + UART8250_LSR) & UART8250_LSR_TEMT))
udelay(1);
}
void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
{
uart8250_mem_wait_to_tx_byte(base_port);
write8(base_port + UART_TBR, data);
write8(base_port + UART8250_TBR, data);
}
void uart8250_mem_tx_flush(unsigned base_port)
@ -70,7 +70,7 @@ void uart8250_mem_tx_flush(unsigned base_port)
int uart8250_mem_can_rx_byte(unsigned base_port)
{
return read8(base_port + UART_LSR) & UART_LSR_DR;
return read8(base_port + UART8250_LSR) & UART8250_LSR_DR;
}
unsigned char uart8250_mem_rx_byte(unsigned base_port)
@ -79,7 +79,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port)
while(i-- && !uart8250_mem_can_rx_byte(base_port))
udelay(1);
if (i)
return read8(base_port + UART_RBR);
return read8(base_port + UART8250_RBR);
else
return 0x0;
}
@ -87,22 +87,22 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port)
void uart8250_mem_init(unsigned base_port, unsigned divisor)
{
/* Disable interrupts */
write8(base_port + UART_IER, 0x0);
write8(base_port + UART8250_IER, 0x0);
/* Enable FIFOs */
write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
write8(base_port + UART8250_FCR, UART8250_FCR_FIFO_EN);
/* Assert DTR and RTS so the other end is happy */
write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
write8(base_port + UART8250_MCR, UART8250_MCR_DTR | UART8250_MCR_RTS);
/* DLAB on */
write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
write8(base_port + UART8250_LCR, UART8250_LCR_DLAB | CONFIG_TTYS0_LCS);
/* Set Baud Rate Divisor. 12 ==> 9600 Baud */
write8(base_port + UART_DLL, divisor & 0xFF);
write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
write8(base_port + UART8250_DLL, divisor & 0xFF);
write8(base_port + UART8250_DLM, (divisor >> 8) & 0xFF);
/* Set to 3 for 8N1 */
write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
write8(base_port + UART8250_LCR, CONFIG_TTYS0_LCS);
}
u32 uart_mem_init(void)