From a85b9a21b281d5aed28c294d82ebaed9df99d0f7 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 4 Apr 2025 19:07:51 -0700 Subject: [PATCH] mb/intel/ptlrvp: Add support for DDR5 configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces support for DDR5 memory configuration on the PTL RVP DDR5 board. It adds the necessary board ID for PTLP_DDR5_RVP and integrates a new DDR5 memory configuration within the variant parameters. The memory configuration includes settings such as resistor values, sagv values, early command training, and DDR5-specific training parameters. Additionally, SPD information retrieval is adapted to accommodate DDR5-specific settings, such as DIMM module topology and SMBus addresses. BUG=none TEST=Boot to OS with PTL RVP DDR5 board and verify memory initialization. Change-Id: I7e3bbb66edcbf4d4a10fcf6899156f125dc3d529 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87179 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) --- src/mainboard/intel/ptlrvp/romstage.c | 36 +++++++++----- .../baseboard/include/baseboard/variants.h | 1 + .../intel/ptlrvp/variants/ptlrvp/memory.c | 47 ++++++++++++++++++- 3 files changed, 70 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/ptlrvp/romstage.c b/src/mainboard/intel/ptlrvp/romstage.c index 1c5297125b..171465ec12 100644 --- a/src/mainboard/intel/ptlrvp/romstage.c +++ b/src/mainboard/intel/ptlrvp/romstage.c @@ -23,11 +23,30 @@ __weak void variant_update_soc_memory_init_params(FSPM_UPD *memupd) /* Nothing to do */ } +static void update_ddr5_sagv_points(FSP_M_CONFIG *m_cfg) +{ + int board_id = get_rvp_board_id(); + + if (board_id != PTLP_DDR5_RVP) + return; + + m_cfg->SaGvFreq[0] = 3200; + m_cfg->SaGvGear[0] = GEAR_4; + + m_cfg->SaGvFreq[1] = 4800; + m_cfg->SaGvGear[1] = GEAR_4; + + m_cfg->SaGvFreq[2] = 5600; + m_cfg->SaGvGear[2] = GEAR_4; + + m_cfg->SaGvFreq[3] = 6400; + m_cfg->SaGvGear[3] = GEAR_4; +} + void mainboard_memory_init_params(FSPM_UPD *memupd) { const struct pad_config *pads; size_t pads_num; - int board_id = get_rvp_board_id(); const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; @@ -40,17 +59,10 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memset(&spd_info, 0, sizeof(spd_info)); variant_get_spd_info(&spd_info); - switch (board_id) { - case PTLP_LP5_T3_RVP: - case PTLP_LP5_T4_RVP: - case GCS_32GB: - case GCS_64GB: - memcfg_init(memupd, mem_config, &spd_info, half_populated); - break; - default: - die("Unknown board id = 0x%x\n", board_id); - break; - } + memcfg_init(memupd, mem_config, &spd_info, half_populated); + + /* Override FSP-M SaGv frequency and gear for DDR5 boards */ + update_ddr5_sagv_points(&memupd->FspmConfig); /* Override FSP-M UPD per board if required. */ variant_update_soc_memory_init_params(memupd); diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h index d44ef98552..0ee09a5835 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h @@ -13,6 +13,7 @@ enum ptl_boardid { PTLP_LP5_T3_RVP = 0x01, PTLP_LP5_T4_RVP = 0x03, + PTLP_DDR5_RVP = 0x04, GCS_32GB = 0x11, GCS_64GB = 0x12, }; diff --git a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c index 3a223e46a7..6a1706fe9f 100644 --- a/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c +++ b/src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c @@ -125,6 +125,24 @@ static const struct mb_cfg lp5_mem_config = { }, }; +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + .resistor = 100, + }, + + .ect = true, /* Early Command Training */ + + .user_bd = BOARD_TYPE_ULT_ULX, + + .lp_ddr_dq_dqs_re_training = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + } +}; + const struct mb_cfg *variant_memory_params(void) { int board_id = get_rvp_board_id(); @@ -136,6 +154,8 @@ const struct mb_cfg *variant_memory_params(void) case GCS_32GB: case GCS_64GB: return &gcs_mem_config; + case PTLP_DDR5_RVP: + return &ddr5_mem_config; default: die("Unknown board id = 0x%x\n", board_id); break; @@ -144,6 +164,29 @@ const struct mb_cfg *variant_memory_params(void) void variant_get_spd_info(struct mem_spd *spd_info) { - spd_info->topo = MEM_TOPO_MEMORY_DOWN; - spd_info->cbfs_index = variant_memory_sku(); + int board_id = get_rvp_board_id(); + + switch (board_id) { + case PTLP_LP5_T3_RVP: + case PTLP_LP5_T4_RVP: + case GCS_32GB: + case GCS_64GB: + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); + break; + case PTLP_DDR5_RVP: + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x0; + spd_info->smbus[1].addr_dimm[0] = 0x50; + spd_info->smbus[1].addr_dimm[1] = 0x0; + spd_info->smbus[2].addr_dimm[0] = 0x52; + spd_info->smbus[2].addr_dimm[1] = 0x0; + spd_info->smbus[3].addr_dimm[0] = 0x52; + spd_info->smbus[3].addr_dimm[1] = 0x0; + break; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } }