Initial checkin for supermicro p4dc6
This also includes a bunch of my pending work including - Updated serial code so we can compile in different serial port speeds - Updates to the build system so that: - Makefile.settings holds all of the settings of the config variables - ldoptions and cpuflags are generated automatically with perl scripts - src/config/Config holds all of the architecture neutral make file settings - Initial work on the P4 including how to use cache as ram - Update to the ioapic code for the P4 because it delivers irqs on the system bus instead of an out of band bus - Updated version of printf that doesn't need an intermediate buffer - logbuf_subr now handles the case when we want to use a log buffer - video_subr handles the preliminary code for writing to a video device. - Pending changes for the L440GX are merged in as well (hopefully I haven't messed then up since they were written).
This commit is contained in:
Eric W. Biederman
parent
be3ebbe61f
commit
a8151ba2cd
53 changed files with 2071 additions and 351 deletions
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@ -36,6 +36,10 @@ EXT(_start): jmp _realstart
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* at 0x18; these are Linux-compatible.
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*/
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#ifndef CACHE_RAM_BASE
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#define CACHE_RAM_BASE 0
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#endif
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/** GDT. we have modified this from the original freebios to make it
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* compatible with linux. This puts text at seg 0x10 and data at 0x18
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*/
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@ -46,16 +50,16 @@ EXT(gdtptr):
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.long gdt /* we know the offset */
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gdt:
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x0, 0x0, 0x0, 0x0
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x0, 0x0, 0x0, 0x0
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.byte 0x00, 0x00, 0x00, 0x00
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.word 0xffff, (CACHE_RAM_BASE & 0xffff) /* flat offset data segment */
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.byte ((CACHE_RAM_BASE >> 16)& 0xff), 0x93, 0xcf, ((CACHE_RAM_BASE >> 24) & 0xff)
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.word 0xffff, 0x0000 /* flat code segment */
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.byte 0x0, 0x9b, 0xcf, 0x0
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.byte 0x00, 0x9b, 0xcf, 0x00
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.word 0xffff, 0x0000 /* flat data segment */
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.byte 0x0, 0x93, 0xcf, 0x0
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.byte 0x00, 0x93, 0xcf, 0x00
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_realstart:
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1
src/cpu/i786/Config
Normal file
1
src/cpu/i786/Config
Normal file
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@ -0,0 +1 @@
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option i786
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39
src/cpu/i786/cache_ram_fini.inc
Normal file
39
src/cpu/i786/cache_ram_fini.inc
Normal file
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@ -0,0 +1,39 @@
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#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
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/* Note: We cannot be running from simulated ram in
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* this code. If we are evil things will happen.
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*/
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/* Disable the cache */
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movl %cr0, %eax
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orl $0x40000000, %eax
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movl %eax, %cr0
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/* Flush everything that is left in the cache,
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* We don't want random writes to memory to occur later on.
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*/
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invd
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/* Disable the cache ram mtrr */
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movl $0x204, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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movl $0x205, %ecx
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xorl %eax, %eax
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xorl %edx, %edx
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wrmsr
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/* Reenable the cache now that the mtrr is cleared */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Reload the normal data segments */
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movw $0x18, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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movw %ax, %fs
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movw %ax, %gs
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#endif
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42
src/cpu/i786/cache_ram_init.inc
Normal file
42
src/cpu/i786/cache_ram_init.inc
Normal file
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@ -0,0 +1,42 @@
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#if defined(CACHE_RAM_BASE) && defined(CACHE_RAM_SIZE)
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/* Disable the cache while we set up the cache ram MTRR */
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movl %cr0, %eax
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orl $0x40000000, %eax
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movl %eax, %cr0
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/* Set up an mtrr in write-back mode over some arbitrary
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* location. As long as we do not get a capacity miss,
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* or a multiprocessor conflict miss this should allow us to
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* function as if we have memory even when it hasn't been
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* enabled yet.
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*/
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movl $0x204, %ecx /* mtrr[0] physical base register */
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xorl %edx, %edx
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movl $(CACHE_RAM_BASE | 0x006), %eax
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wrmsr
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movl $0x205, %ecx /* mtrr[0] physical mask register */
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movl $0x0000000f, %edx
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movl $(~(CACHE_RAM_SIZE - 1) | 0x800), %eax
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wrmsr
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/* Reenable the cache now that the mtrr is set up */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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/* Force cache ram area into cache */
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movl $CACHE_RAM_BASE, %esi
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movl $(CACHE_RAM_BASE + CACHE_RAM_SIZE), %edi
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1: movl (%esi), %eax
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addl $4, %esi
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movl %eax, (%esi)
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cmpl %esi, %edi
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jnz 1b
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/* Load a different set of data segments */
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movw $0x08, %ax
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movw %ax, %ds
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movw %ax, %es
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movw %ax, %ss
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#endif
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25
src/cpu/i786/cache_ram_start.inc
Normal file
25
src/cpu/i786/cache_ram_start.inc
Normal file
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@ -0,0 +1,25 @@
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/* copy data segment from FLASH ROM to CACHE */
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movl $(EXT(_ldata) - CACHE_RAM_BASE), %esi
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movl $EXT(_data), %edi
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movl $(EXT(_eldata) - CACHE_RAM_BASE), %ecx
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subl %esi, %ecx
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jz 1f /* should not happen */
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rep
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movsb
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1:
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/** clear bss */
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movl $EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz 1f
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xorl %eax, %eax
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rep
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stosb
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1:
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/* set new stack */
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movl $(_stack + STACK_SIZE), %esp
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call cache_ram_start
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108
src/cpu/i786/earlymtrr.inc
Normal file
108
src/cpu/i786/earlymtrr.inc
Normal file
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@ -0,0 +1,108 @@
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#include <cpu/p6/mtrr.h>
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/* The fixed and variable MTRRs are powered-up with random values, clear them to
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* MTRR_TYPE_UNCACHABLE for safty reason
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*/
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earlymtrr_start:
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xorl %eax, %eax # clear %eax and %edx
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xorl %edx, %edx #
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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#ifdef MEMORY_HOLE
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set_fixed_mtrr:
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/* enable Write Back Cache for 0-640KB */
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movl $MTRRfix64K_00000_MSR, %ecx
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rdmsr
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movl $0x06060606, %edx
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movl $0x06060606, %eax
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wrmsr
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movl $MTRRfix16K_80000_MSR, %ecx
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rdmsr
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movl $0x06060606, %edx
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movl $0x06060606, %eax
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wrmsr
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#endif /* MEMORY_HOLE */
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set_var_mtrr:
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#if 0
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/* enable caching for 0 - 128MB using variable mtrr */
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movl $0x200, %ecx
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rdmsr
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andl $0xfffffff0, %edx
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orl $0x00000000, %edx
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andl $0x00000f00, %eax
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orl $0x00000006, %eax
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wrmsr
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movl $0x201, %ecx
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rdmsr
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andl $0xfffffff0, %edx
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orl $0x0000000f, %edx
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andl $0x000007ff, %eax
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orl $0xf0000800, %eax
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wrmsr
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#endif
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write protect caching so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | 0x005), %eax
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wrmsr
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movl $0x203, %ecx
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movl $0x0000000f, %edx
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movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
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wrmsr
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#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
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enable_mtrr:
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $0x2ff, %ecx
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xorl %edx, %edx
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#ifdef MEMORY_HOLE
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/* Enable Fixed and Variable MTRRs */
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movl $0x00000c00, %eax
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#else
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/* Enable Variable MTRRs */
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movl $0x00000800, %eax
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#endif /* MEMORY_HOLE */
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wrmsr
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff,%eax
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movl %eax, %cr0
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jmp earlymtrr_end
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fixed_mtrr_msr:
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.long 0x250, 0x258, 0x259
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.long 0x268, 0x269, 0x26A
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.long 0x26B, 0x26C, 0x26D
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.long 0x26E, 0x26F
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var_mtrr_msr:
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.long 0x200, 0x201, 0x202, 0x203
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.long 0x204, 0x205, 0x206, 0x207
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.long 0x208, 0x209, 0x20A, 0x20B
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.long 0x20C, 0x20D, 0x20E, 0x20F
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.long 0x000 /* NULL, end of table */
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earlymtrr_end:
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@ -109,6 +109,7 @@ static unsigned char fixed_mtrr_values[][4] = {
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{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
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};
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#else
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static unsigned char fixed_mtrr_values[][4] = {
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/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
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{RAM, RAM, RAM, RAM}, {RAM, RAM, RAM, RAM},
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@ -143,6 +144,7 @@ static unsigned char fixed_mtrr_values[][4] = {
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/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
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{ROM, ROM, ROM, ROM}, {ROM, ROM, ROM, ROM},
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};
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#endif
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#undef FB
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