erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Setup the MTRRs in stage1 so that memory and cache are available throughout

Browse source 
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Marc Jones 2009-02-10 22:40:10 +00:00
commit a794edb17b
6 changed files with 169 additions and 99 deletions
Download patch file Download diff file Expand all files Collapse all files

51
include/arch/x86/amd/k8/k8.h
View file

@ -695,56 +695,9 @@ void showallroutes(int level, u32 dev);
/* k8/reset_test.c */
void distinguish_cpu_resets(unsigned nodeid);
/* These are functions that MUST be inlined as we can not use a stack -- CAR or real ram */
/* by yhlu 6.2005 */
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
__asm__ volatile (
/* We don't need cache as ram for now on */
/* disable cache */
"movl %cr0, %eax\n\t"
"orl $(0x1<<30),%eax\n\t"
"movl %eax, %cr0\n\t"
/* clear sth */
"movl $0x269, %ecx\n\t" /* fix4k_c8000*/
"xorl %edx, %edx\n\t"
"xorl %eax, %eax\n\t"
"wrmsr\n\t"
#if CONFIG_CARSIZE > 0x8000
"movl $0x268, %ecx\n\t" /* fix4k_c0000*/
"wrmsr\n\t"
#endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
"movl $0xC0010010, %ecx\n\t"
// "movl $SYSCFG_MSR, %ecx\n\t"
"rdmsr\n\t"
"andl $(~(3<<18)), %eax\n\t"
// "andl $(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t"
"wrmsr\n\t"
/* Set the default memory type and disable fixed and enable variable MTRRs */
"movl $0x2ff, %ecx\n\t"
// "movl $MTRRdefType_MSR, %ecx\n\t"
"xorl %edx, %edx\n\t"
/* Enable Variable and Disable Fixed MTRRs */
"movl $0x00000800, %eax\n\t"
"wrmsr\n\t"
/* enable cache */
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
);
}
void disable_cache_as_ram_bsp(void);
inline __attribute__((always_inline)) void disable_cache_as_ram(void);
void set_top_mem_ap(unsigned tom_k, unsigned tom2_k);
#endif /* ! ASSEMBLY */
#endif /* AMD_K8_H */

2
include/arch/x86/cpu.h
View file

@ -267,7 +267,7 @@ static inline void clear_init_ram(void)
}
void set_init_ram_access(void);
void set_mtrr_ram_access(void);
void * bottom_of_stack(void);
EXPORT_SYMBOL(bottom_of_stack);

4
include/arch/x86/mtrr.h
View file

@ -37,6 +37,10 @@ void x86_setup_mtrrs(unsigned address_bits);
int x86_mtrr_check(void);
void stage1_set_var_mtrr(unsigned long reg, unsigned long base,
unsigned long size, unsigned long type);
void stage1_set_fix_mtrr(u32 reg, u8 type);
void stage1_set_var_mtrr_x(unsigned long reg, u32 base_lo, u32 base_hi,
u32 size_lo, u32 size_hi, unsigned long type);
#endif