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UPSTREAM: google/eve: Use rt5663 interrupt as GpioInt instead of PIRQ

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The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.

Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller.  This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.

BUG=b:35585307
BRANCH=none
TEST=test on Eve that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.

Change-Id: Idba470851244dcdabb6919b12c513b2597c81c16
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 887e7936f8
Original-Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18836
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456305
This commit is contained in:
Duncan Laurie 2017-03-15 11:34:04 -07:00 • committed by chrome-bot
commit a75c946295
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/eve/devicetree.cb
View file

@ -274,7 +274,7 @@ chip soc/intel/skylake
register "hid" = ""10EC5663""
register "name" = ""RT53""
register "desc" = ""Realtek RT5663""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)"
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)"
register "probed" = "1"
device i2c 13 on end
end

2
src/mainboard/google/eve/gpio.h
View file

@ -129,7 +129,7 @@ static const struct pad_config gpio_table[] = {
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CS# */ PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */
/* ISH_SPI_CS# */ PAD_CFG_GPI(GPP_D9, NONE, PLTRST), /* HP_IRQ_GPIO */
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* SPKR_RST_L */
/* ISH_SPI_MISO */ PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST), /* SPKR_INT_L */
/* ISH_SPI_MOSI */ PAD_CFG_TERM_GPO(GPP_D12, 1, 20K_PU, DEEP), /* EN_PP3300_DX_CAM */