erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

arch/x86: Unify GDT entries

Browse source 
Currently there are 3 GDTs (Global Descriptor Tables) being used on x86:
- preRAM (gdt_init.S)
- SMM (smm_stub.S)
- RAM (c_start.S)

They have different layouts and thus different offsets for the segments
being used in assembly code. Stop using different GDT segments and
ensure that for ROM (preRAM + SMM) and RAM (ramstage) the segments
match. RAM will have additional entries, not found in pre RAM GDT,
but the segments for protected mode and 64-bit mode now match in
all stages.

This allows to use the same defines in all stages. It also drops the
need to know in which stage the code is compiled and it's no longer
necessary to switch the code segment between stages.

While at it fix the comments in the ramstage GDT and drop unused
declarations from header files, always set the accessed bit and drop
GDT_CODE_ACPI_SEG.

Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Patrick Rudolph 2025-04-10 08:51:55 +02:00 • committed by Matt DeVillier
commit a6be271e63
14 changed files with 89 additions and 135 deletions
Download patch file Download diff file Expand all files Collapse all files

12
src/security/intel/stm/StmPlatformSmm.c
View file

@ -4,6 +4,7 @@
#include <security/intel/stm/SmmStm.h>
#include <security/intel/stm/StmPlatformResource.h>
#include <security/tpm/tspi.h>
#include <cpu/x86/gdt.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
@ -11,7 +12,6 @@
#include <console/console.h>
#include <stdbool.h>
#include <stdint.h>
#include <arch/rom_segs.h>
/*
* Load STM image to MSEG
@ -109,11 +109,11 @@ void setup_smm_descriptor(void *smbase, int32_t apic_id, int32_t entry32_off)
psd->acpi_rsdp = 0;
psd->bios_hw_resource_requirements_ptr =
(uint64_t)((uintptr_t)get_stm_resource());
psd->smm_cs = ROM_CODE_SEG;
psd->smm_ds = ROM_DATA_SEG;
psd->smm_ss = ROM_DATA_SEG;
psd->smm_other_segment = ROM_DATA_SEG;
psd->smm_tr = SMM_TASK_STATE_SEG;
psd->smm_cs = GDT_CODE_SEG;
psd->smm_ds = GDT_DATA_SEG;
psd->smm_ss = GDT_DATA_SEG;
psd->smm_other_segment = GDT_DATA_SEG;
psd->smm_tr = GDT_TASK_STATE_SEG;
// At this point the coreboot smm_stub is relative to the default
// smbase and not the one for the smi handler in tseg. So we have

6
src/security/intel/txt/getsec_enteraccs.S
View file

@ -3,7 +3,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <arch/ram_segs.h>
#include <cpu/x86/gdt.h>
#include "getsec_mtrr_setup.inc"
@ -257,10 +257,10 @@ cond_clear_var_mtrrs:
lgdt -48(%ebp)
/* Set cs */
ljmp $RAM_CODE_SEG, $1f
ljmp $GDT_CODE_SEG, $1f
1:
/* Fix segment registers */
movl $RAM_DATA_SEG, %eax
movl $GDT_DATA_SEG, %eax
movl %eax, %ds
movl %eax, %es
movl %eax, %ss