From a6bb17f6141b0f7c22969af8ec58edcea2da9fe4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 13 Jun 2017 14:12:38 +0200 Subject: [PATCH] UPSTREAM: src/soc/intel/common: Don't allow user to change PCIe BAR BUG=none BRANCH=none TEST=none Change-Id: I0890bbb69183f2ec11c0c2fc3114ac29ee7321d3 Signed-off-by: Patrick Georgi Original-Commit-Id: 48d6b76d53a43c6924ed27303651aed5c6c6f34c Original-Change-Id: I254549057552be93611afa8ca52d22be220fe3dc Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/20178 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Philippe Mathieu-Daud Original-Reviewed-by: Sumeet R Pawnikar Reviewed-on: https://chromium-review.googlesource.com/539214 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/soc/intel/common/block/systemagent/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 01a4f8e201..2084a38692 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -4,7 +4,7 @@ config SOC_INTEL_COMMON_BLOCK_SA Intel Processor common System Agent support config MMCONF_BASE_ADDRESS - hex "PCI MMIO Base Address" + hex default 0xe0000000 config SA_PCIEX_LENGTH