diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 57233a9833..1ab1eb3748 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -80,6 +80,9 @@ static acpi_cstate_t cstate_map[] = {
 
 void acpi_init_gnvs(global_nvs_t *gnvs)
 {
+	/* Set unknown wake source */
+	gnvs->pm1i = -1;
+
 	/* CPU core count */
 	gnvs->pcnt = dev_count_cpu();
 
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl
index b384cea1ec..a201c03d50 100644
--- a/src/soc/intel/baytrail/acpi/globalnvs.asl
+++ b/src/soc/intel/baytrail/acpi/globalnvs.asl
@@ -52,6 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TPMP,	 8,	// 0x12 - TPM Present and Enabled
 	TLVL,	 8,	// 0x13 - Throttle Level
 	PPCM,	 8,	// 0x14 - Maximum P-state usable by OS
+	PM1I,	 32,	// 0x15 - System Wake Source - PM1 Index
 
 	/* Device Config */
 	Offset (0x20),
diff --git a/src/soc/intel/baytrail/acpi/platform.asl b/src/soc/intel/baytrail/acpi/platform.asl
index e0693928fa..e32880ef9b 100644
--- a/src/soc/intel/baytrail/acpi/platform.asl
+++ b/src/soc/intel/baytrail/acpi/platform.asl
@@ -71,3 +71,8 @@ Method(_WAK,1)
 	Return(Package(){0,0})
 }
 
+Method (_SWS)
+{
+	/* Index into PM1 for device that caused wake */
+	Return (\PM1I)
+}
diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h
index 5bc1b0eb5a..b1561f74f9 100644
--- a/src/soc/intel/baytrail/baytrail/nvs.h
+++ b/src/soc/intel/baytrail/baytrail/nvs.h
@@ -43,7 +43,8 @@ typedef struct {
 	u8	tpmp; /* 0x12 - TPM Present and Enabled */
 	u8	tlvl; /* 0x13 - Throttle Level */
 	u8	ppcm; /* 0x14 - Maximum P-state usable by OS */
-	u8	rsvd1[11];
+	u32	pm1i; /* 0x15 - System Wake Source - PM1 Index */
+	u8	rsvd1[7];
 
 	/* Device Config */
 	u8	s5u0; /* 0x20 - Enable USB0 in S5 */
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 9fe6c27dfe..0cc932700f 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -36,6 +36,7 @@
 #include <baytrail/nvs.h>
 #include <baytrail/pattrs.h>
 #include <baytrail/pci_devs.h>
+#include <baytrail/pmc.h>
 #include <baytrail/ramstage.h>
 
 /* Global PATTRS */
@@ -131,6 +132,32 @@ static inline void set_acpi_sleep_type(int val)
 #endif
 }
 
+/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
+static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+{
+	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
+	uint16_t pm1;
+
+	if (!ps)
+		return;
+
+	pm1 = ps->pm1_sts & ps->pm1_en;
+
+	/* Scan for first set bit in PM1 */
+	for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
+		if (pm1 & 1)
+			break;
+		pm1 >>= 1;
+	}
+
+	/* If unable to determine then return -1 */
+	if (gnvs->pm1i >= 16)
+		gnvs->pm1i = -1;
+
+	printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
+	       gnvs->pm1i);
+}
+
 static void s3_resume_prepare(void)
 {
 	global_nvs_t *gnvs;
@@ -148,6 +175,8 @@ static void s3_resume_prepare(void)
 	}
 
 	set_acpi_sleep_type(3);
+
+	s3_save_acpi_wake_source(gnvs);
 }
 
 void baytrail_init_pre_device(void)