From a69f91b5817cf8da90d8036b7afd5d6bc4be9b21 Mon Sep 17 00:00:00 2001 From: Appukuttan V K Date: Tue, 3 Feb 2026 14:35:22 +0530 Subject: [PATCH] mb/google/ocelot: Update GT VR controller configuration This patch implements the recommended BIOS power delivery settings described in Intel WW03 2026 Wildcat Lake platform message of the week (844458). Key changes: - Enable acoustic noise mitigation with SLEW_FAST_4 for GT domain - Enable fast package C-state ramp disable for GT domain - Update fast_vmode_i_trip to 25A (was 38A) - Enable GT VR fast voltage mode and CEP BUG=b:467349691 TEST=Build ocelot and verify that the system boots to UI with the updated parameters. [SPEW ] IccMax[1]:0x90 [SPEW ] EnableFastVmode[1]:0x1 [SPEW ] IccLimit[1]:0x64 [SPEW ] CepEnable[1]:0x1 [SPEW ] FastPkgCRampDisable[1]:0x1 [SPEW ] SlowSlewRate[1]:0x1 [SPEW ] AcousticNoiseMitigation:0x1 Change-Id: I76cefc79457c6bcfb250ba3525c501a126b526fb Signed-off-by: Appukuttan V K Reviewed-on: https://review.coreboot.org/c/coreboot/+/91073 Tested-by: build bot (Jenkins) Reviewed-by: P, Usha Reviewed-by: Matt DeVillier --- .../variants/baseboard/ocelot/devicetree.cb | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb index 9391ac9d37..23b276e15a 100644 --- a/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb +++ b/src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb @@ -29,6 +29,12 @@ chip soc/intel/pantherlake register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + # Acoustic Noise settings and slew rate configuration: + # Slew rate for GT Domain: Fast/4 + register "enable_acoustic_noise_mitigation" = "true" + register "disable_fast_pkgc_ramp[VR_DOMAIN_GT]" = "true" + register "slow_slew_rate_config[VR_DOMAIN_GT]" = "SLEW_FAST_4" + # Enable SAGv register "sagv" = "SAGV_ENABLED" @@ -61,15 +67,14 @@ chip soc/intel/pantherlake # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true" - # Reference: 858124 Power Delivery Guide Rev1p0, 830097 Powermap Rev1p1 + # Reference: 844458 MOW WW03 # fast_vmode_i_trip values are derived from ICCMax with a safety margin. # ITRIP_NOM is approximately 0.70 of ICCMax # TODO: Update with actual i_trip values. - + register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" + register "cep_enable[VR_DOMAIN_GT]" = "true" register "fast_vmode_i_trip[WCL_CORE]" = "{ - [VR_DOMAIN_IA] = 35 * 4, - [VR_DOMAIN_GT] = 35 * 4, - [VR_DOMAIN_SA] = 24 * 4 + [VR_DOMAIN_GT] = 25 * 4, }" register "serial_io_uart_mode" = "{