mb/dell: Convert OptiPlex 3050 into variant

To minimize code duplication when adding the new "optiplex_5040" port
CB:88735, the "optiplex_3050" should be turned into a variant first.

Naming of the template inspired by "ifdtool --platform quirk" and recent
"sklkbl_thinkpads" commit. However it's naming is not limmited to its
CPU support since some Coffee Lake (Refresh) CPUs are already tested!

Currently chose a more common name "desktops" although yet only Dell
OptiPlex units are supported Inspiron, Vostro or even Precision desktops
running the same chipset(s) and code should be foreseen.

Open to any other naming / convention suggestions?

Patch stages:
patch1: add variant template with duplicated code some specialized files
        but full devicetree.cb as overridetree.cb wont build as variant!
patch2: edit Kconfig(.name) and Makefile.mk to include both variants
        trim each overridetree.cb specific & derive common devicetree.cb
        builds both variants only tested and verified "optiplex_5040"
patch3: remove "optiplex_5040" variant so this only turns into a variant
        containing the converted "optiplex_3050"
patch12 customized gpio between 3050 and 5040 use gpio.c vs gpio.h

Further patches mostly rebasing.

TEST=Checksum BUILD_TIMELESS=1 matches if original build adds 1 ramstage
     linked file to variant folder! See comments howto verify checksum.

Change-Id: I16e3b92104f515b334afaacfed740a3b71f5b048
Signed-off-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88726
Reviewed-by: Máté Kukri <km@mkukri.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/dell/optiplex_3050/Makefile.mk

@@ -1,12 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-bootblock-y += sch5555_ec.c
-
-romstage-y += romstage.c
-
-ramstage-y += ramstage.c
-ramstage-y += sch5555_ec.c
-ramstage-y += hda_verb.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/dell/sklkbl_desktops/Kconfig

@@ -1,9 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-if BOARD_DELL_OPTIPLEX_3050
+config BOARD_DELL_SKLKBL_DESKTOPS_COMMON
-
+	bool
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
 	select AZALIA_USE_LEGACY_VERB_TABLE
 	select BOARD_ROMSIZE_KB_16384
 	select HAVE_ACPI_RESUME
@@ -20,19 +18,31 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_KABYLAKE
 	select SUPERIO_SMSC_SCH555x
 
+config BOARD_DELL_OPTIPLEX_3050
+	bool
+	select BOARD_DELL_SKLKBL_DESKTOPS_COMMON
+
+if BOARD_DELL_SKLKBL_DESKTOPS_COMMON
+
+config MAINBOARD_DIR
+	default "dell/sklkbl_desktops"
+
+config MAINBOARD_PART_NUMBER
+	default "OptiPlex 3050 Micro" if BOARD_DELL_OPTIPLEX_3050
+
+config VARIANT_DIR
+	default "optiplex_3050" if BOARD_DELL_OPTIPLEX_3050
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config INTEL_GMA_VBT_FILE
+	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/data.vbt"
+
 config CBFS_SIZE
 	default 0x900000
 
-config MAINBOARD_DIR
-	default "dell/optiplex_3050"
-
-config MAINBOARD_PART_NUMBER
-	default "OptiPlex 3050 Micro"
-
-config INTEL_GMA_VBT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/data.vbt"
-
 config DIMM_SPD_SIZE
-	default 512	# DDR4
+	default 512 if BOARD_DELL_OPTIPLEX_3050	# DDR4
 
 endif

src/mainboard/dell/sklkbl_desktops/Makefile.mk

@@ -0,0 +1,15 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c
+bootblock-y += sch5555_ec.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += sch5555_ec.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

src/mainboard/dell/sklkbl_desktops/board_info.txt

@@ -0,0 +1,5 @@
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/dell/sklkbl_desktops/bootblock.c

@@ -4,7 +4,7 @@
 #include <device/pnp_ops.h>
 #include <soc/gpio.h>
 #include <superio/smsc/sch555x/sch555x.h>
-#include "include/early_gpio.h"
+#include "../../../include/variant/gpio.h"
 #include "sch5555_ec.h"
 
 struct ec_init_entry {
@@ -88,7 +88,7 @@ static void bootblock_ec_init(void)
 
 void bootblock_mainboard_early_init(void)
 {
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+	variant_configure_early_gpios();
 
 	// Super I/O early init will map Runtime and EMI registers
 	sch555x_early_init(GLOBAL_DEV);

src/mainboard/dell/sklkbl_desktops/devicetree.cb

@@ -0,0 +1,75 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
+
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+	device domain 0 on
+
+		device ref peg0 off end
+
+		device ref igpu on
+			register "PrimaryDisplay" = "Display_iGFX"
+		end
+
+		device ref south_xhci on end
+
+		# ME interface is 'off' to avoid HECI reset delay due to HAP
+		device ref heci1 off end
+
+		device ref sata on end
+
+		device ref pcie_rp5 off end
+
+		device ref pcie_rp8 off end
+
+		device ref pcie_rp9 off end
+
+		device ref pcie_rp17 off end
+
+		device ref pcie_rp21 off end
+
+		# UART0 is exposed on test points on the bottom of the board
+		device ref uart0 on
+			register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
+		end
+
+		device ref lpc_espi on
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			# I/O decode for EMI/Runtime registers
+			register "gen1_dec" = "0x007c0a01"
+
+			# SCH5553
+			chip superio/smsc/sch555x
+				device pnp 2e.0 on		# EMI
+					io 0x60 = 0xa00
+				end
+				device pnp 2e.1 off end		# 8042
+				device pnp 2e.7 on		# UART1
+					io 0x60 = 0x3f8
+					irq 0x0f = 2
+					irq 0x70 = 4
+				end
+				device pnp 2e.8 off end		# UART2
+				device pnp 2e.c on		# LPC interface
+					io 0x60 = 0x2e
+				end
+				device pnp 2e.a on		# Runtime registers
+					io 0x60 = 0xa40
+				end
+				device pnp 2e.b  off end	# Floppy Controller
+				device pnp 2e.11 off end	# Parallel Port
+			end
+
+		end
+
+		device ref hda on end
+
+		device ref smbus on end
+
+		device ref gbe off end
+	end
+end

src/mainboard/dell/sklkbl_desktops/include/variant/gpio.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif

src/mainboard/dell/sklkbl_desktops/ramstage.c

@@ -5,12 +5,12 @@
 #include <cpu/x86/msr.h>
 #include <soc/gpio.h>
 #include <soc/ramstage.h>
-#include "include/gpio.h"
+#include "../../../include/variant/gpio.h"
 #include "sch5555_ec.h"
 
 void mainboard_silicon_init_params(FSP_SIL_UPD *params)
 {
-	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+	variant_configure_gpios();
 }
 
 #define FORM_FACTOR_MICRO	0

src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/early_gpio.c

@@ -1,11 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+/*
 #ifndef __OPTIPLEX_3050_EARLY_GPIO_H__
 #define __OPTIPLEX_3050_EARLY_GPIO_H__
+*/
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include "../../../include/variant/gpio.h"
 
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),	/* UART0_RXD */
 	PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),	/* UART0_TXD */
 };
 
-#endif
+// #endif
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/gpio.c

@@ -1,7 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef __OPTIPLEX_3050_GPIO_H__
+#include <soc/gpe.h>
-#define __OPTIPLEX_3050_GPIO_H__
+#include <soc/gpio.h>
+#include "../../../include/variant/gpio.h"
+
+/* #ifndef __OPTIPLEX_3050_GPIO_H__ #define __OPTIPLEX_3050_GPIO_H__ */
 
 static const struct pad_config gpio_table[] = {
 
@@ -238,4 +241,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPP_I10, DN_20K, PLTRST, NF1),			/* DDPD_CTRLDATA */
 };
 
-#endif
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+// #endif

src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb

@@ -1,15 +1,8 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip soc/intel/skylake
-	register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_EN_LAN_WAKE_PIN"
-
-	# Enable Enhanced Intel SpeedStep
-	register "eist_enable" = "1"
 
 	device domain 0 on
-		device ref igpu on
-			register "PrimaryDisplay" = "Display_iGFX"
-		end
 
 		device ref south_xhci on
 			register "usb2_ports" = "{
@@ -29,22 +22,9 @@ chip soc/intel/skylake
 			}"
 		end
 
-		# ME interface is 'off' to avoid HECI reset delay due to HAP
-		device ref heci1 off end
-
 		device ref sata on
-			register "SataSalpSupport" = "1"
+			register "SataSalpSupport"			= "1"
-			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[0]"			= "1"
-		end
-
-		# M.2 SSD
-		device ref pcie_rp21 on
-			register "PcieRpClkReqSupport[20]"              = "true"
-			register "PcieRpClkReqNumber[20]"               = "3"
-			register "PcieRpAdvancedErrorReporting[20]"     = "1"
-			register "PcieRpLtrEnable[20]"                  = "true"
-			register "PcieRpClkSrcNumber[20]"               = "3"
-			register "PcieRpHotPlug[20]"                    = "1"
 		end
 
 		# Realtek LAN
@@ -59,42 +39,15 @@ chip soc/intel/skylake
 			register "PcieRpHotPlug[7]"			= "1"
 		end
 
-		# UART0 is exposed on test points on the bottom of the board
+		# M.2 SSD
-		device ref uart0 on
+		device ref pcie_rp21 on
-			register "SerialIoDevMode[PchSerialIoIndexUart0]" = "PchSerialIoPci"
+			register "PcieRpClkReqSupport[20]"              = "true"
+			register "PcieRpClkReqNumber[20]"               = "3"
+			register "PcieRpAdvancedErrorReporting[20]"     = "1"
+			register "PcieRpLtrEnable[20]"                  = "true"
+			register "PcieRpClkSrcNumber[20]"               = "3"
+			register "PcieRpHotPlug[20]"                    = "1"
 		end
 
-		device ref lpc_espi on
-			register "serirq_mode" = "SERIRQ_CONTINUOUS"
-
-			# I/O decode for EMI/Runtime registers
-			register "gen1_dec" = "0x007c0a01"
-
-			# SCH5553
-			chip superio/smsc/sch555x
-				device pnp 2e.0 on		# EMI
-					io 0x60 = 0xa00
-				end
-				device pnp 2e.1 off end		# 8042
-				device pnp 2e.7 on		# UART1
-					io 0x60 = 0x3f8
-					irq 0x0f = 2
-					irq 0x70 = 4
-				end
-				device pnp 2e.8 off end 	# UART2
-				device pnp 2e.c on		# LPC interface
-					io 0x60 = 0x2e
-				end
-				device pnp 2e.a on		# Runtime registers
-					io 0x60 = 0xa40
-				end
-				device pnp 2e.b  off end	# Floppy Controller
-				device pnp 2e.11 off end	# Parallel Port
-			end
-		end
-
-		device ref hda on end
-
-		device ref smbus on end
 	end
 end