From a644690615b539bef40fe26a88f05a49a9b3167a Mon Sep 17 00:00:00 2001 From: "jinkun.hong" Date: Wed, 21 Jan 2015 15:47:25 +0800 Subject: [PATCH] rk3288: LPDDR3 reboot test fail tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate this single, but the max value we can set is 7, can not meet the standard.So, now we send the Mode Register Set command manual,and we can add the delay manual. BUG=chrome-os-partner:34608 TEST=loop reboot BRANCH=veyron Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d Signed-off-by: jinkun.hong Reviewed-on: https://chromium-review.googlesource.com/242176 Reviewed-by: Julius Werner (cherry picked from commit b60a4de6ff3ad3720c2c06ed7de03ed942360e6c) Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/243125 --- src/soc/rockchip/rk3288/sdram.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index d330f99d6e..cda36be05d 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -998,12 +998,29 @@ void sdram_init(const struct rk3288_sdram_params *sdram_params) writel(POWER_UP_START, &ddr_pctl_regs->powctl); while (!(readl(&ddr_pctl_regs->powstat) & POWER_UP_DONE)) ; - send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0); - udelay(1); - send_command(ddr_pctl_regs, 3, PREA_CMD, 0); memory_init(ddr_publ_regs, sdram_params->dramtype); move_to_config_state(ddr_publ_regs, ddr_pctl_regs); + + if (sdram_params->dramtype == LPDDR3) { + send_command(ddr_pctl_regs, 3, DESELECT_CMD, 0); + udelay(1); + send_command(ddr_pctl_regs, 3, PREA_CMD, 0); + udelay(1); + send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(63) | + LPDDR2_OP(0xFC)); + udelay(1); + send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(1) | + LPDDR2_OP(sdram_params->phy_timing.mr[1])); + udelay(1); + send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(2) | + LPDDR2_OP(sdram_params->phy_timing.mr[2])); + udelay(1); + send_command(ddr_pctl_regs, 3, MRS_CMD, LPDDR2_MA(3) | + LPDDR2_OP(sdram_params->phy_timing.mr[3])); + udelay(1); + } + set_bandwidth_ratio(channel, sdram_params->ch[channel].bw); /* * set cs