diff --git a/src/northsouthbridge/sis/630/630_regs.inc b/src/northsouthbridge/sis/630/630_regs.inc
index 962f88345f..f0220f08e1 100644
--- a/src/northsouthbridge/sis/630/630_regs.inc
+++ b/src/northsouthbridge/sis/630/630_regs.inc
@@ -36,7 +36,7 @@ northbridge_init_table:
 	.byte	0x07,	0x00	# 	
 	.byte	0x0D,	0x20	# Master Latency Timer = 32 PCI CLCK
 
-	/* SiS 630 specific registers. See SiS 630 Reconnaded Registers Setting */
+	/* SiS 630 specific registers. See SiS 630 Registers Recommended Setting */
 	
 	/* Host Control Interface */
 	.byte	0x50,	0x9C	#
diff --git a/src/northsouthbridge/sis/630/630s_regs.inc b/src/northsouthbridge/sis/630/630s_regs.inc
index 6b66674b62..b3da29eae0 100644
--- a/src/northsouthbridge/sis/630/630s_regs.inc
+++ b/src/northsouthbridge/sis/630/630s_regs.inc
@@ -27,7 +27,7 @@
  * $Id$
  */
 
-pci_init_table:
+northbridge_init_table:
 #		Reg.	Value
 	/* generic PCI configuration space */
 	.byte	0x04,	0x07	# Turn on Bus Master,
@@ -36,7 +36,7 @@ pci_init_table:
 	.byte	0x07,	0x00	# 	
 	.byte	0x0D,	0x20	# Master Latency Timer = 32 PCI CLCK
 
-	/* SiS 630 specific registers. See SiS 630 Reconnaded Registers Setting */
+	/* SiS 630 specific registers. See SiS 630 Registers Recommended Setting */
 	
 	/* Host Control Interface */
 	.byte	0x50,	0x7E	#
@@ -49,19 +49,19 @@ pci_init_table:
 	.byte	0x54,	0x00	# 0x00 -> 66/100 MHZ, 0x08 -> 133 MHZ
 	.byte	0x55,	0x05	# 0x05 -> 66/100 MHZ, 0x01 -> 133 MHZ
 	.byte	0x56,	0x80	# 0x00 -> 66  MHZ,    0x80 -> 100/133 MHZ
-	.byte	0x57,	0x00	# 0x00 -> 100 MHZ     0x01 -> 133 MHZ
+	.byte	0x57,	0x00	# 0x00 -> 66  MHZ     0x01 -> 100/133 MHZ
 
 	/* Pre-driver Slew Rate/Current Driving Control */
 	.byte	0x58,	0x00	#
 	.byte	0x59,	0x05	#
-	.byte	0x5A,	0x51	#
+	.byte	0x5A,	0x51	# 0x51 -> 1 or 2 DIMM, 0x55 -> 3 DIMM 
 	.byte	0x5B,	0x00	#
 
 	.byte	0x65,	0x00	# Use DIMM 0 for SMA
 
 	/* MISC Control */
 	.byte	0x6A,	0xC6	#
-	.byte	0x6B,	0x00	# 0x00 -> 66/133 MHZ, 0x01 -> 100 MHZ
+	.byte	0x6B,	0x00	#
 	.byte	0x6C,	0x2f	# 0x2E -> 66 MHZ, 0x20 -> 100 MHZ, 0x2C -> 133 MHZ
  
 	/* PCI Interface */
@@ -102,4 +102,4 @@ pci_init_table:
 	.byte	0xCA,	0x00
 	.byte	0xCB,	0x00
 
-pci_init_table_end:
\ No newline at end of file
+northbridge_init_table_end:
diff --git a/src/northsouthbridge/sis/630/ipl.S b/src/northsouthbridge/sis/630/ipl.S
index 361e7afba3..ec32c6480f 100644
--- a/src/northsouthbridge/sis/630/ipl.S
+++ b/src/northsouthbridge/sis/630/ipl.S
@@ -212,7 +212,7 @@ sis630ipl_start:
 	outb	%al, $0x2f
 
 	xorw	%sp, %sp			# clear %sp
-	xorw	%dx, %dx			# clear $dx, start of RAM
+	xorw	%dx, %dx			# clear %dx, start of RAM
 	movw	$0x800, %si			# point %si to CDSN Data area
 	movw	$0x1000, %di			# point %di to CDSN Control area
 	movw	$DOC_SPL_START_BLK, %bp		# start page of LinuxBIOS
diff --git a/src/northsouthbridge/sis/630/raminit.inc b/src/northsouthbridge/sis/630/raminit.inc
index 9fe73c8109..45556d1c9a 100644
--- a/src/northsouthbridge/sis/630/raminit.inc
+++ b/src/northsouthbridge/sis/630/raminit.inc
@@ -55,7 +55,7 @@ write_northbridge_register:
 	movl	$NORTH_BRIDGE_BASE_ADDR, %edx
 
 write_common:
-	movl	%eax, %ebx			# Save %ax to %cx.
+	movl	%eax, %ebx			# Save %eax to %ebx.
 
 	movzbl	%bh, %eax			# add register address to
 	addl	%edx, %eax			# PCI base address
diff --git a/src/northsouthbridge/sis/630/southbridge.c b/src/northsouthbridge/sis/630/southbridge.c
index e8ebf4aff9..cd4bd0f14c 100644
--- a/src/northsouthbridge/sis/630/southbridge.c
+++ b/src/northsouthbridge/sis/630/southbridge.c
@@ -70,6 +70,27 @@ void nvram_on()
 #endif
 }
 
+/* serial_irq_fixup: Enable Serial Interrupt. Serial interrupt is the IRQ line from SiS 950
+ *	LPC to Host Controller. Serial IRQ is neceressary for devices on SiS 950
+ *	ie.e floppy, COM, LPT etc
+ */
+static void
+serial_irq_fixedup(void)
+{
+	struct pci_dev *pcidev;
+
+	pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, (void *)NULL);
+	if (pcidev != NULL) {
+		/* enable Serial Interrupt (SIRQ) */
+		pci_write_config_byte(pcidev, 0x70, 0x80); 
+		// skip the SMI, inta, etc. stuff. 
+		// enable IRQs 7 to 1
+		pci_write_config_byte(pcidev, 0x72, 0xfd);
+		// enable IRQs 15 to 8
+		pci_write_config_byte(pcidev, 0x73, 0xff);
+	}
+}
+
 static void
 acpi_fixup(void)
 {
@@ -80,17 +101,6 @@ acpi_fixup(void)
 		unsigned char val;
 		unsigned short acpibase = 0xc000, temp;
 		int i;
-		// put symbolic names in here soon ... so much typing, so little time. 
-
-		// now set up legacy serial interrupts
-		// that doesn't mean serial ports -- it's a serial interrupt
-		// line from the superio (LPC)
-		// first, enable them. 
-		pci_write_config_byte(pcidev, 0x70, 0x80); 
-		// skip the SMI, inta, etc. stuff. 
-		// enable IRQs 7 to 1
-		pci_write_config_byte(pcidev, 0x72, 0xfd);
-		pci_write_config_byte(pcidev, 0x73, 0xff);
 
 		// the following is to turn off software watchdogs. 
 		// we co-op the address space from c000-cfff here. Temporarily. 
@@ -115,16 +125,7 @@ acpi_fixup(void)
 		       inw(acpibase+0x56));
 		printk(KERN_INFO "acpi status: byte at 0x4b is 0x%x\n", 
 		       inb(acpibase + 0x4b));
-#if 0
-		// this hangs anyway, so what's the point. 
-		for(i = 0; i < 0x63; i += 16) {
-			int j; 
-			printk(KERN_INFO "0x%x: ", i);
-			for(j = 0; (j < 16) && ((j + i) < 0x63); j++)
-				printk(KERN_INFO "%02x ", inb(acpibase + i + j));
-			printk(KERN_INFO "\n");
-		}
-#endif
+
 		// now that it's on, get in there and call off the dogs. 
 		// that's the recommended thing to do if MD40 iso on. 
 		outw(0, acpibase + 0x56);
@@ -173,6 +174,7 @@ final_southbridge_fixup()
 	}
 #endif /* OLD_KERNEL_HACK */
 
+	serial_irq_fixedup();
 	acpi_fixup();
 
 	printk(KERN_INFO "Southbridge fixup done for SIS 503\n");