erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

pistachio: modify memory layout

Browse source 
With the code now running on the FPGA board it makes sense to correct
the memory layout definitions to match the actual hardware.

Note that the latest FPGA board firmware introduced support of the
additional 128KB of SRAM (called GRAM) at base address of 0x9a000000.

These are still interim values, which will be tweaked when the actual
bring up board is available.

BRANCH=none
BUG=chrome-os-partner:31438
TEST=the code put into SPI NOR flash boots all the way to ramstage.

Change-Id: I50183c2d5f9017801d5c8a7a7addf08efa492b35
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vadim Bendebury 2014-11-11 20:14:47 -08:00 • committed by chrome-internal-fetch
commit a6378be5cd
1 changed files with 10 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

19
src/soc/imgtec/pistachio/include/soc/memlayout.ld
View file

@ -21,18 +21,19 @@
#include <arch/header.ld>
/* TODO: This should be revised by someone who understands the SoC better. */
SECTIONS
{
CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */
DRAM_START(0x80000000)
RAMSTAGE(0x80000000, 128K)
/* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */
BOOTBLOCK(0x9B000000, 16K)
ROMSTAGE(0x9B004000, 40K)
STACK(0x9B00E000, 6K)
PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K)
/* GRAM becomes the SRAM. */
SRAM_START(0x9a000000)
BOOTBLOCK(0x9a000000, 16K)
ROMSTAGE(0x9a004000, 32K)
STACK(0x9a01c000, 8K)
PRERAM_CBMEM_CONSOLE(0x9a01e000, 8K)
SRAM_END(0x9a020000)
/* Let's use SRAM for CBFS cache. */
CBFS_CACHE(0x9b000000, 64K)
}