tegra132: add support for TZ carveout

The TrustZone carveout needs to be taken into account when
determining the memory layout. However, things are complicated
by the fact that TZ carveout registers are not accessible by
the AVP.

BUG=chrome-os-partner:30572
BRANCH=None
TEST=Built and booted to end of ramstage. Noted that denver cores
     can read TZ registers while AVP doesn't bother.

Change-Id: I2d2d27e33a334bf639af52260b99d8363906c646
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/207835
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Tom Warren <twarren@nvidia.com>

src/soc/nvidia/tegra132/addressmap.c

@@ -23,6 +23,7 @@
 #include <console/console.h>
 #include <soc/addressmap.h>
 #include <soc/display.h>
+#include <soc/id.h>
 #include "mc.h"
 #include "sdram.h"
 
@@ -70,6 +71,13 @@ void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib)
 
 	switch (id) {
 	case CARVEOUT_TZ:
+		/* AVP does not have access to the TZ carveout registers. */
+		if (context_avp())
+			return;
+		carveout_from_regs(base_mib, size_mib,
+					read32(&mc->security_cfg0),
+					0,
+					read32(&mc->security_cfg1));
 		break;
 	case CARVEOUT_SEC:
 		carveout_from_regs(base_mib, size_mib,

src/soc/nvidia/tegra132/cbmem.c

@@ -25,6 +25,13 @@ void *cbmem_top(void)
 	static uintptr_t addr;
 	size_t fb_size;
 
+	/*
+	 * FIXME(adurbin): The TZ registers are not accessible to the AVP.
+	 * Therefore, if there is a TZ carveout then it needs to be handled
+	 * here while executing on the AVP in order to properly place the
+	 * CBMEM region.
+	 */
+
 	/* CBMEM starts downwards from the framebuffer. */
 	if (addr == 0)
 		addr = framebuffer_attributes(&fb_size);

src/soc/nvidia/tegra132/include/soc/id.h

@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__
+#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__
+
+
+#include <arch/io.h>
+#include <soc/addressmap.h>
+
+static inline int context_avp(void)
+{
+	const uint32_t avp_id = 0xaaaaaaaa;
+	void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;
+
+	return read32(uptag) == avp_id;
+}
+
+#endif /* define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ID_H__ */

src/soc/nvidia/tegra132/mc.h

@@ -42,7 +42,9 @@ struct tegra_mc_regs {
 	uint32_t emem_adr_cfg_bank_mask_0;	/* 0x64 */
 	uint32_t emem_adr_cfg_bank_mask_1;	/* 0x68 */
 	uint32_t emem_adr_cfg_bank_mask_2;	/* 0x6c */
-	uint32_t rsvd_0x70[8];			/* 0x70 */
+	uint32_t security_cfg0;			/* 0x70 */
+	uint32_t security_cfg1;			/* 0x74 */
+	uint32_t rsvd_0x78[6];			/* 0x78 */
 	uint32_t emem_arb_cfg;			/* 0x90 */
 	uint32_t emem_arb_outstanding_req;	/* 0x94 */
 	uint32_t emem_arb_timing_rcd;		/* 0x98 */