From a4bc3131a5fa0787b7024e5115ff3f9ec33ad291 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Wed, 25 Feb 2026 10:33:14 -0800 Subject: [PATCH] soc/intel/common/feature/gspi: Add common devfn mapping Add a common implementation of gspi_soc_bus_to_devfn() to reduce code duplication across multiple Intel SoC platforms. This implementation uses the SOC_GSPI_DEVFN(n) macro which must be defined by each platform in their soc/pci_devs.h header to map GSPI bus numbers to PCI device and function values. This change enables consolidation of nearly identical gspi.c files from Alder Lake, Meteor Lake, Panther Lake, Tiger Lake, Jasper Lake, Elkhart Lake, Cannon Lake, and Skylake platforms. The implementation leverages the existing CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX Kconfig option and includes compile-time assertions to ensure the configuration is within supported limits (up to 7 GSPI controllers). Change-Id: I776cebd70968fd4b8bbab176bca0a446a0cc76ab Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/91322 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/soc/intel/common/feature/gspi/Kconfig | 9 ++++ src/soc/intel/common/feature/gspi/Makefile.mk | 3 ++ .../intel/common/feature/gspi/gspi_devfn.c | 44 +++++++++++++++++++ 3 files changed, 56 insertions(+) create mode 100644 src/soc/intel/common/feature/gspi/Kconfig create mode 100644 src/soc/intel/common/feature/gspi/Makefile.mk create mode 100644 src/soc/intel/common/feature/gspi/gspi_devfn.c diff --git a/src/soc/intel/common/feature/gspi/Kconfig b/src/soc/intel/common/feature/gspi/Kconfig new file mode 100644 index 0000000000..4ac4e47693 --- /dev/null +++ b/src/soc/intel/common/feature/gspi/Kconfig @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN + bool + help + Common GSPI device function to bus mapping implementation. + SoCs using this must define SOC_GSPI_DEVFN(n) macro in their + pci_devs.h and CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX in their + Kconfig. diff --git a/src/soc/intel/common/feature/gspi/Makefile.mk b/src/soc/intel/common/feature/gspi/Makefile.mk new file mode 100644 index 0000000000..6ac84bac54 --- /dev/null +++ b/src/soc/intel/common/feature/gspi/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +all-$(CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN) += gspi_devfn.c diff --git a/src/soc/intel/common/feature/gspi/gspi_devfn.c b/src/soc/intel/common/feature/gspi/gspi_devfn.c new file mode 100644 index 0000000000..23cdaaaf14 --- /dev/null +++ b/src/soc/intel/common/feature/gspi/gspi_devfn.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +/* + * Ensure the platform defines SOC_GSPI_DEVFN(n) macro to map GSPI bus numbers + * to their PCI device/function values. The macro should be defined in the + * platform's soc/pci_devs.h header. + */ + +_Static_assert(CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX <= 7, + "CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX greater than 7 is not supported."); + +int gspi_soc_bus_to_devfn(unsigned int gspi_bus) +{ + switch (gspi_bus) { + case 0: + return SOC_GSPI_DEVFN(0); + case 1: + return SOC_GSPI_DEVFN(1); +#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 2 + case 2: + return SOC_GSPI_DEVFN(2); +#endif +#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 3 + case 3: + return SOC_GSPI_DEVFN(3); +#endif +#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 4 + case 4: + return SOC_GSPI_DEVFN(4); +#endif +#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 5 + case 5: + return SOC_GSPI_DEVFN(5); +#endif +#if CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX > 6 + case 6: + return SOC_GSPI_DEVFN(6); +#endif + } + return -1; +}