erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: soc/intel/skylake: Add missing PCH_DEV_PCIE* definitions

Browse source 
This is required to add wake sources for PCIE PME events.

BUG=b:37088992

Change-Id: I46f4b244510ba5201566a4cd2c7e2e205b065137
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1cf7f86d92
Original-Change-Id: Ideecdf133908b0819d7d993e1c7df1a6578cb77d
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19924
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517931
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-05-25 00:14:35 -07:00 • committed by chrome-bot
commit a4b1a63d9f
1 changed files with 6 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/soc/intel/skylake/include/soc/pci_devs.h
View file

@ -111,12 +111,18 @@
#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
#define PCH_DEV_SLOT_PCIE_1 0x1d
#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
#define PCH_DEV_SLOT_STORAGE 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(STORAGE, 0)