erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Migrate 206ax to SMM_MODULES

Browse source 
This gets rid of ugly tseg_relocate for bd82x6x.

This is backport of 29ffa54969 to bd82x6x.

Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Vladimir Serbinenko 2015-05-28 16:04:17 +02:00
commit a3e41c0896
10 changed files with 385 additions and 187 deletions
Download patch file Download diff file Expand all files Collapse all files

51
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -43,7 +43,6 @@
#define NMI_OFF 0
#define ENABLE_ACPI_MODE_IN_COREBOOT 0
#define TEST_SMM_FLASH_LOCKDOWN 0
typedef struct southbridge_intel_bd82x6x_config config_t;
@ -427,58 +426,20 @@ static void enable_clock_gating(device_t dev)
RCBA32_OR(0x3564, 0x3);
}
#if CONFIG_HAVE_SMI_HANDLER
static void pch_lock_smm(struct device *dev)
static void pch_set_acpi_mode(void)
{
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
if (!acpi_is_wakeup_s3()) {
if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(0x1e, 0xb2); // Disable ACPI mode
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#endif
}
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
#endif
}
#endif
static void pch_disable_smm_only_flashing(struct device *dev)
{
@ -572,9 +533,7 @@ static void lpc_init(struct device *dev)
pch_disable_smm_only_flashing(dev);
#if CONFIG_HAVE_SMI_HANDLER
pch_lock_smm(dev);
#endif
pch_set_acpi_mode();
pch_fixups(dev);
}

5
src/southbridge/intel/bd82x6x/pch.h
View file

@ -66,6 +66,11 @@ void intel_pch_finalize_smm(void);
#include "chip.h"
void pch_enable(device_t dev);
#endif
/* These helpers are for performing SMM relocation. */
void southbridge_smm_init(void);
void southbridge_trigger_smi(void);
void southbridge_clear_smi_status(void);
int pch_silicon_revision(void);
int pch_silicon_type(void);
int pch_silicon_supported(int type, int rev);

99
src/southbridge/intel/bd82x6x/smi.c
View file

@ -28,10 +28,6 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include "pch.h"
#include "northbridge/intel/sandybridge/sandybridge.h"
extern unsigned char _binary_smm_start;
extern unsigned char _binary_smm_end;
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
@ -228,15 +224,18 @@ static void smi_set_eos(void)
outb(reg8, pmbase + SMI_EN);
}
extern uint8_t smm_relocation_start, smm_relocation_end;
static void smm_relocate(void)
void southbridge_smm_init(void)
{
u32 smi_en;
u16 pm1_en;
u32 gpe0_en;
printk(BIOS_DEBUG, "Initializing SMM handler...");
#if CONFIG_ELOG
/* Log events from chipset before clearing */
pch_log_state();
#endif
printk(BIOS_DEBUG, "Initializing southbridge SMI...");
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
@ -249,10 +248,6 @@ static void smm_relocate(void)
return;
}
/* copy the SMM relocation code */
memcpy((void *)0x38000, &smm_relocation_start,
&smm_relocation_end - &smm_relocation_start);
printk(BIOS_DEBUG, "\n");
dump_smi_status(reset_smi_status());
dump_pm1_status(reset_pm1_status());
@ -301,7 +296,10 @@ static void smm_relocate(void)
smi_en |= EOS | GBL_SMI_EN;
outl(smi_en, pmbase + SMI_EN);
}
void southbridge_trigger_smi(void)
{
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@ -320,79 +318,18 @@ static void smm_relocate(void)
outb(0x00, 0xb2);
}
static int smm_handler_copied = 0;
static void smm_install(void)
void southbridge_clear_smi_status(void)
{
device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
u32 smm_base = 0xa0000;
struct ied_header ied = {
.signature = "INTEL RSVD",
.size = IED_SIZE,
.reserved = {0},
};
/* The first CPU running this gets to copy the SMM handler. But not all
* of them.
*/
if (smm_handler_copied)
return;
smm_handler_copied = 1;
/* enable the SMM memory window */
pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
#if CONFIG_SMM_TSEG
smm_base = pci_read_config32(dev, TSEG) & ~1;
#endif
/* copy the real SMM handler */
printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
memcpy((void *)smm_base, &_binary_smm_start,
(size_t)(&_binary_smm_end - &_binary_smm_start));
/* copy the IED header into place */
if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
/* Top of TSEG region */
smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
smm_base);
memcpy((void *)smm_base, &ied, sizeof(ied));
}
wbinvd();
/* close the SMM memory window and enable normal SMM */
pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
}
void smm_init(void)
{
#if CONFIG_ELOG
/* Log events from chipset before clearing */
pch_log_state();
#endif
/* Put SMM code to 0xa0000 */
smm_install();
/* Put relocation code to 0x38000 and relocate SMBASE */
smm_relocate();
/* We're done. Make sure SMIs can happen! */
/* Clear SMI status */
reset_smi_status();
/* Clear PM1 status */
reset_pm1_status();
/* Set EOS bit so other SMIs can occur. */
smi_set_eos();
}
void smm_lock(void)
{
/* LOCK the SMM memory window and enable normal SMM.
* After running this function, only a full reset can
* make the SMM registers writable again.
*/
printk(BIOS_DEBUG, "Locking SMM.\n");
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
D_LCK | G_SMRAME | C_BASE_SEG);
}
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
/*

72
src/southbridge/intel/bd82x6x/smihandler.c
View file

@ -31,10 +31,6 @@
#include "nvs.h"
/* We are using PCIe accesses for now
* 1. the chipset can do it
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <arch/pci_mmio_cfg.h>
#include <southbridge/intel/bd82x6x/me.h>
@ -54,28 +50,12 @@ static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
static global_nvs_t *gnvs = (global_nvs_t *)0x0;
static global_nvs_t *gnvs;
global_nvs_t *smm_get_gnvs(void)
{
return gnvs;
}
#if CONFIG_SMM_TSEG
static u32 tseg_base = 0;
u32 smi_get_tseg_base(void)
{
if (!tseg_base)
tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
return tseg_base;
}
void tseg_relocate(void **ptr)
{
/* Adjust pointer with TSEG base */
if (*ptr && *ptr < (void*)smi_get_tseg_base())
*ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
}
#endif
static void alt_gpi_mask(u16 clr, u16 set)
{
u16 alt_gp = inw(pmbase + ALT_GP_SMI_EN);
@ -424,7 +404,7 @@ static void xhci_sleep(u8 slp_typ)
}
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_sleep(void)
{
u8 reg8;
u32 reg32;
@ -439,8 +419,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
outb(tmp70, 0x70);
outb(tmp72, 0x72);
void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
reg8 &= ~SLP_SMI_EN;
@ -455,8 +433,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
xhci_sleep(slp_typ);
/* Do any mainboard sleep handling */
tseg_relocate((void **)&mainboard_sleep);
mainboard_sleep(slp_typ-2);
mainboard_smi_sleep(slp_typ-2);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
@ -532,13 +509,11 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
{
em64t101_smm_state_save_area_t *state;
u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET;
int node;
/* Check all nodes looking for the one that issued the IO */
for (node = 0; node < CONFIG_MAX_CPUS; node++) {
state = (em64t101_smm_state_save_area_t *)
(base - (node * 0x400));
state = smm_get_save_state(node);
/* Check for Synchronous IO (bit0==1) */
if (!(state->io_misc_info & (1 << 0)))
@ -587,11 +562,10 @@ static void southbridge_smi_gsmi(void)
static int mainboard_finalized = 0;
static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_apmc(void)
{
u32 pmctrl;
u8 reg8;
int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@ -657,11 +631,10 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
#endif
}
tseg_relocate((void **)&mainboard_apmc);
mainboard_apmc(reg8);
mainboard_smi_apmc(reg8);
}
static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_pm1(void)
{
u16 pm1_sts;
@ -682,7 +655,7 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_
}
}
static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_gpe0(void)
{
u32 gpe0_sts;
@ -690,17 +663,15 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state
dump_gpe0_status(gpe0_sts);
}
static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_gpi(void)
{
void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi;
u16 reg16;
reg16 = inw(pmbase + ALT_GP_SMI_STS);
outw(reg16, pmbase + ALT_GP_SMI_STS);
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
tseg_relocate((void **)&mainboard_gpi);
mainboard_gpi(reg16);
mainboard_smi_gpi(reg16);
if (reg16)
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
@ -708,7 +679,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_
outw(reg16, pmbase + ALT_GP_SMI_STS);
}
static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_mc(void)
{
u32 reg32;
@ -723,7 +694,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s
static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_tco(void)
{
u32 tco_sts;
@ -760,7 +731,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
}
}
static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_periodic(void)
{
u32 reg32;
@ -773,7 +744,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s
printk(BIOS_DEBUG, "Periodic SMI.\n");
}
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
static void southbridge_smi_monitor(void)
{
#define IOTRAP(x) (trap_sts & (1 << x))
u32 trap_sts, trap_cycle;
@ -827,8 +798,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
#undef IOTRAP
}
typedef void (*smi_handler_t)(unsigned int node,
smm_state_save_area_t *state_save);
typedef void (*smi_handler_t)(void);
static smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
@ -870,7 +840,7 @@ static smi_handler_t southbridge_smi[32] = {
* @param node
* @param state_save
*/
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
void southbridge_smi_handler(void)
{
int i, dump = 0;
u32 smi_sts;
@ -887,15 +857,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
#if CONFIG_SMM_TSEG
smi_handler_t handler = (smi_handler_t)
((u8*)southbridge_smi[i] +
smi_get_tseg_base());
if (handler)
handler(node, state_save);
#else
southbridge_smi[i](node, state_save);
#endif
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
"handler available.\n", i);