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- One more code sync up, change the startup code.

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This commit is contained in:
Eric W. Biederman 2002-10-25 22:57:21 +00:00
commit a3c4d998ee
18 changed files with 190 additions and 217 deletions
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3
src/cpu/i386/entry16.inc
View file

@ -26,6 +26,7 @@ it with the version available from LANL.
*/
/* .section ".rom.text" */
#include <arch/rom_segs.h>
.code16
.globl EXT(_start)
.type EXT(_start), @function
@ -93,7 +94,7 @@ EXT(_start):
movl %eax, %cr0
/* Now that we are in protected mode jump to a 32 bit code segment. */
data32 ljmp $0x10, $__protected_start
data32 ljmp $ROM_CODE_SEG, $__protected_start
/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
* at 0x18; these are Linux-compatible.

50
src/cpu/i386/entry32.inc
View file

@ -1,66 +1,40 @@
/* For starting linuxBIOS in protected mode */
#include <arch/rom_segs.h>
#include <arch/cache_ram.h>
/* .section ".rom.text" */
.code32
/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
* at 0x18; these are Linux-compatible.
*/
/** GDT. we have modified this from the original freebios to make it
* compatible with linux. This puts text at seg 0x10 and data at 0x18
*/
.align 4
.globl EXT(gdtptr)
gdt:
EXT(gdtptr):
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
.word 0
gdt:
// selgdt 0
.word 0x0000, 0x0000 /* dummy */
.byte 0x00, 0x00, 0x00, 0x00
// selgdt 8
/* flat cache ram offset data segment */
.word 0xffff, _cache_ram_seg_base_low
.byte _cache_ram_seg_base_middle, 0x93, 0xcf
.byte _cache_ram_seg_base_high
// selgdt 0x10
/* flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
//selgdt 0x18
/* flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
//selgdt 0x20
#if 0 /* FIXME make the cache as ram code work again */
/* flat rom offset code segment */
.word 0xffff, _rom_code_seg_base_low
.byte _rom_code_seg_base_middle, 0x9b, 0xcf
.byte _rom_code_seg_base_high
/* flat cache ram offset data segment */
.word 0xffff, _cache_ram_seg_base_low
.byte _cache_ram_seg_base_middle, 0x93, 0xcf
.byte _cache_ram_seg_base_high
#endif
#if defined(CONFIG_VGABIOS) && (CONFIG_VGABIOS == 1)
// from monty:
/* 0x00009a00,0000ffffULL, 20h: 16-bit 64k code at 0x00000000 */
/* 0x00009200,0000ffffULL 28h: 16-bit 64k data at 0x00000000 */
// selgdt 0x28
/*16-bit 64k code at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x9a, 0, 0
// selgdt 0x30
/*16-bit 64k data at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x92, 0, 0
#endif // defined(CONFIG_VGABIOS) && (CONFIG_VGABIOS == 1)
gdt_end:
@ -80,12 +54,12 @@ gdt_end:
EXT(protected_start):
lgdt %cs:gdtptr
ljmp $0x10, $__protected_start
ljmp $ROM_CODE_SEG, $__protected_start
__protected_start:
intel_chip_post_macro(0x10) /* post 10 */
movw $0x18, %ax
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss

2
src/cpu/i386/entry32.lds
View file

@ -1,3 +1,4 @@
/*
_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
_cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff;
_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
@ -7,6 +8,7 @@
_rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff;
_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
_rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff;
*/

2
src/cpu/i786/cache_ram_fini.inc
View file

@ -30,7 +30,7 @@
movl %eax, %cr0
/* Reload the normal data segments */
movw $0x18, %ax
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss

3
src/cpu/i786/cache_ram_init.inc
View file

@ -54,9 +54,8 @@ start_cacheram: .string "Start cache ram\r\n"
cmpl %esi, %edi
jnz 1b
intel_chip_post_macro(0x02)
/* Load a different set of data segments */
movw $0x08, %ax
movw $CACHE_RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss

6
src/cpu/i786/cache_ram_start.inc
View file

@ -34,11 +34,11 @@
* - I change teh code segments back to my normal segment with
* a 4GB limit and a base address of 0.
*/
ljmp $0x20, $___cache_ram_code_start
ljmp $CACHE_RAM_CODE_SEG, $___cache_ram_code_start
.globl __cache_ram_code_start
__cache_ram_code_start:
lcall $0x20, $cache_ram_start
ljmp $0x10, $__cache_ram_code_done
lcall $CACHE_RAM_CODE_SEG, $cache_ram_start
ljmp $ROM_CODE_SEG, $__cache_ram_code_done
.globl __cache_ram_code_done
__cache_ram_code_done:

2
src/cpu/p6/cache_ram_fini.inc
View file

@ -30,7 +30,7 @@
movl %eax, %cr0
/* Reload the normal data segments */
movw $0x18, %ax
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss

2
src/cpu/p6/cache_ram_init.inc
View file

@ -41,7 +41,7 @@
jnz 1b
/* Load a different set of data segments */
movw $0x08, %ax
movw $CACHE_RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss

11
src/cpu/p6/microcode.c
View file

@ -304,7 +304,7 @@ static void display_cpuid_update_microcode(void)
{
unsigned int eax, ebx, ecx, edx;
unsigned int pf, rev, sig, val[2];
unsigned int x86_model, i;
unsigned int x86_model, x86_family, i;
struct microcode *m;
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
@ -312,15 +312,16 @@ static void display_cpuid_update_microcode(void)
cpuid(1, &eax, &ebx, &ecx, &edx);
rdmsr(0x8B, val[0], rev);
x86_model = (eax >>4) & 0x0f;
x86_family = (eax >>8) & 0x0f;
sig = eax;
pf = 0;
if (x86_model >= 5) {
if ((x86_model >= 5)||(x86_family>6)) {
rdmsr(0x17, val[0], val[1]);
pf = 1 << ((val[1] >> 18) & 7);
}
printk_info("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
sig, pf, rev);
printk_debug("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
sig, pf, rev);
m = (void *)&microcode_updates;
for(i = 0; i < sizeof(microcode_updates)/sizeof(struct microcode); i++) {
@ -336,6 +337,6 @@ static void display_cpuid_update_microcode(void)
void p6_cpufixup(struct mem_range *mem)
{
printk_info("Updating microcode\n");
printk_debug("Updating microcode\n");
display_cpuid_update_microcode();
}