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rockchip/rk3399: Configure USB3 controller work in USB2 only mode

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During the USB2 only mode, the Type-C PHY will be held in reset
and only USB2 part logic of USB3 OTG controller and PHY may be
used over the USB2 pins on the Type-C connector to support Low,
Full and High-speed USB operation.

BRANCH=none
BUG=chrome-os-partner:56425
TEST=Go to recovery mode, plug a Type-C USB drive containing
chrome OS image into both ports in all orientations, check if
system can boot form USB.

Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad
Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/385837
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Liangfeng Wu 2016-09-15 17:16:54 +08:00 • committed by chrome-bot
commit a37ccc5b60
1 changed files with 15 additions and 0 deletions
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15
src/soc/rockchip/rk3399/usb.c
View file

@ -17,6 +17,9 @@
#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/clock.h>
#include <soc/grf.h>
#include <soc/soc.h>
#include <soc/usb.h>
/* SuperSpeed over Type-C is hard. We don't care about speed in firmware: just
@ -86,12 +89,24 @@ static void setup_dwc3(struct rockchip_usb_dwc3 *dwc3)
void reset_usb_otg0(void)
{
/* Keep whole USB OTG0 controller in reset, then
* configure controller to work in USB 2.0 only mode. */
write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 5));
write32(&rk3399_grf->usb3otg0_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 5));
printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG0\n");
reset_dwc3(rockchip_usb_otg0_dwc3);
}
void reset_usb_otg1(void)
{
/* Keep whole USB OTG1 controller in reset, then
* configure controller to work in USB 2.0 only mode. */
write32(&cru_ptr->softrst_con[18], RK_SETBITS(1 << 6));
write32(&rk3399_grf->usb3otg1_con1, RK_CLRSETBITS(0xf << 12, 1 << 0));
write32(&cru_ptr->softrst_con[18], RK_CLRBITS(1 << 6));
printk(BIOS_DEBUG, "Starting DWC3 reset for USB OTG1\n");
reset_dwc3(rockchip_usb_otg1_dwc3);
}