From a2e7d84725739843a1ed1868fcadebb60477a6dc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 5 Aug 2014 14:03:17 -0500 Subject: [PATCH] ryu: enable vboot firmware verification Add the supporting Kconfig options and infrastructure for performing vboot firmware verification. BUG=chrome-os-partner:30784 BRANCH=None TEST=Built and ran on ryu into depthcharge noting vboot paths being taken. Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/211134 Reviewed-by: Tom Warren Reviewed-by: Furquan Shaikh --- configs/config.rush_ryu | 2 + src/mainboard/google/rush_ryu/Kconfig | 22 ++++++ src/mainboard/google/rush_ryu/chromeos.c | 89 ++++++++++++++++++++++++ src/mainboard/google/rush_ryu/romstage.c | 2 + 4 files changed, 115 insertions(+) create mode 100644 src/mainboard/google/rush_ryu/chromeos.c diff --git a/configs/config.rush_ryu b/configs/config.rush_ryu index f1f94d9299..e530eb3540 100644 --- a/configs/config.rush_ryu +++ b/configs/config.rush_ryu @@ -5,3 +5,5 @@ CONFIG_CONSOLE_SERIAL=y CONFIG_CONSOLE_CBMEM=y CONFIG_MTS_DIRECTORY="3rdparty/mainboard/google/rush" CONFIG_BOOTROM_SDRAM_INIT=y +CONFIG_VBOOT_VERIFY_FIRMWARE=y +CONFIG_FLASHMAP_OFFSET=0x00200000 diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 5c0dee2192..bb5ba931b4 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -22,8 +22,14 @@ if BOARD_GOOGLE_RUSH_RYU config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ID_SUPPORT + select CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_I2C + select EC_SOFTWARE_SYNC + select SPI_FLASH select SOC_NVIDIA_TEGRA132 select MAINBOARD_HAS_BOOTBLOCK_INIT + select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR string @@ -67,4 +73,20 @@ config BOOT_MEDIA_SPI_CHIP_SELECT help Which chip select to use for boot media. +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x2 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config EC_GOOGLE_CHROMEEC_I2C_BUS + hex + default 1 + endif # BOARD_GOOGLE_RUSH_RYU diff --git a/src/mainboard/google/rush_ryu/chromeos.c b/src/mainboard/google/rush_ryu/chromeos.c new file mode 100644 index 0000000000..401cf9372e --- /dev/null +++ b/src/mainboard/google/rush_ryu/chromeos.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* TODO(adurbin): add lid switch */ + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO(R1)); +} diff --git a/src/mainboard/google/rush_ryu/romstage.c b/src/mainboard/google/rush_ryu/romstage.c index 47c3df66ee..4365502cdc 100644 --- a/src/mainboard/google/rush_ryu/romstage.c +++ b/src/mainboard/google/rush_ryu/romstage.c @@ -35,6 +35,8 @@ static const struct pad_config padcfgs[] = { /* EC on I2C2 */ PAD_CFG_SFIO(GEN2_I2C_SCL, PINMUX_INPUT_ENABLE, I2C2), PAD_CFG_SFIO(GEN2_I2C_SDA, PINMUX_INPUT_ENABLE, I2C2), + /* WP_L */ + PAD_CFG_GPIO_INPUT(KB_ROW1, PINMUX_PULL_NONE), }; static void configure_clocks(void)