erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Allow to build romstage sources inside the bootblock

Browse source 
Having a separate romstage is only desirable:
 - with advanced setups like vboot or normal/fallback
 - boot medium is slow at startup (some ARM SOCs)
 - bootblock is limited in size (Intel APL 32K)

When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.

This is controlled via a Kconfig option.

TESTED: works on qemu x86, arm and aarch64 with and without VBOOT.

Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2021-05-29 08:10:49 +02:00 • committed by Felix Held
commit a2bc2540c2
46 changed files with 118 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/arch/arm64/romstage.c
View file

@ -11,6 +11,7 @@
__weak void platform_romstage_main(void) { /* no-op, for bring-up */ }
__weak void platform_romstage_postram(void) { /* no-op */ }
#if CONFIG(SEPARATE_ROMSTAGE)
void main(void)
{
timestamp_add_now(TS_ROMSTAGE_START);
@ -20,6 +21,7 @@ void main(void)
exception_init();
romstage_main();
}
#endif
void __noreturn romstage_main(void)
{

6
src/arch/x86/Makefile.inc
View file

@ -161,12 +161,12 @@ endif # CONFIG_ARCH_VERSTAGE_X86_32 / CONFIG_ARCH_VERSTAGE_X86_64
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)
romstage-y += assembly_entry.S
romstage-y += romstage.c
romstage-$(CONFIG_SEPARATE_ROMSTAGE) += assembly_entry.S
romstage-$(CONFIG_SEPARATE_ROMSTAGE) += romstage.c
romstage-y += boot.c
romstage-$(CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES) += breakpoint.c
romstage-y += post.c
romstage-y += gdt_init.S
romstage-$(CONFIG_SEPARATE_ROMSTAGE) += gdt_init.S
romstage-y += cpu_common.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S

2
src/arch/x86/assembly_entry.S
View file

@ -53,7 +53,7 @@ _start:
#endif
#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
|| (ENV_SEPARATE_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
/* Wait for a JTAG debugger to break in and set EBX non-zero */
xor %ebx, %ebx

4
src/arch/x86/car.ld
View file

@ -75,7 +75,7 @@
RECORD_SIZE(bss)
#endif
#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
#if ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
_shadow_size = (_ebss - _car_region_start) >> 3;
REGION(asan_shadow, ., _shadow_size, ARCH_POINTER_ALIGN_SIZE)
#endif
@ -144,7 +144,7 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_SEPARATE_VERSTAGE)
#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_SEPARATE_ROMSTAGE || ENV_SEPARATE_VERSTAGE)
_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
#endif

2
src/arch/x86/memcpy.c
View file

@ -8,7 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n)
{
unsigned long d0, d1, d2;
#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
(ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE))
check_memory_region((unsigned long)src, n, false, _RET_IP_);
check_memory_region((unsigned long)dest, n, true, _RET_IP_);

2
src/arch/x86/memlayout.ld
View file

@ -26,7 +26,7 @@ SECTIONS
/* Relocated at runtime in cbmem so the address does not matter. */
RAMSTAGE(64M, 8M)
#elif ENV_ROMSTAGE
#elif ENV_SEPARATE_ROMSTAGE
/* The 1M size is not allocated. It's just for basic size checking.
* Link at 32MiB address and rely on cbfstool to relocate to XIP. */
ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)

2
src/arch/x86/memmove_32.c
View file

@ -12,7 +12,7 @@ void *memmove(void *dest, const void *src, size_t n)
int d0, d1, d2, d3, d4, d5;
char *ret = dest;
#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
(ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE))
check_memory_region((unsigned long)src, n, false, _RET_IP_);
check_memory_region((unsigned long)dest, n, true, _RET_IP_);

2
src/arch/x86/memset.c
View file

@ -14,7 +14,7 @@ void *memset(void *dstpp, int c, size_t len)
int d0;
unsigned long int dstp = (unsigned long int)dstpp;
#if (ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
#if (ENV_SEPARATE_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)) || \
(ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE))
check_memory_region((unsigned long)dstpp, len, true, _RET_IP_);
#endif