From a1dd6bfc22cebeea4a623b1e222dbd709224e92d Mon Sep 17 00:00:00 2001
From: Kilian Krause <kilian.krause@siemens.com>
Date: Wed, 4 Jun 2025 10:22:20 +0200
Subject: [PATCH] mb/siemens/mc_rpl1: Adjust PCIe settings in devicetree

This mainboard does not utilize CKLREQ signaling for PCIe. Only three
PCIe clock sources are used on this board. Configure the Root Ports
accordingly to hardware implementation.

Change-Id: If4241a05dd0c5df258d4a7018d71a21f7d314e69
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88879
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/siemens/mc_rpl/devicetree.cb    | 67 -------------------
 .../mc_rpl/variants/mc_rpl1/overridetree.cb   | 55 ++++++++++++++-
 2 files changed, 54 insertions(+), 68 deletions(-)

diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb
index fd582dfbb1..8b701d7638 100644
--- a/src/mainboard/siemens/mc_rpl/devicetree.cb
+++ b/src/mainboard/siemens/mc_rpl/devicetree.cb
@@ -32,65 +32,6 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"	# USB3/2 Type A port3
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
 
-	# Enable PCH PCIE RP 5 using CLK 2
-	register "pch_pcie_rp[PCH_RP(5)]" = "{
-		.clk_src = 2,
-		.clk_req = 2,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# Enable PCH PCIE RP 6 using CLK 5
-	register "pch_pcie_rp[PCH_RP(6)]" = "{
-		.clk_src = 5,
-		.clk_req = 5,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
-	register "pch_pcie_rp[PCH_RP(8)]" = "{
-                .clk_src = 7,
-                .clk_req = 7,
-                .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
-                .PcieRpL1Substates = L1_SS_L1_2,
-		.pcie_rp_detect_timeout_ms = 50,
-	}"
-
-	# Enable PCH PCIE RP 9 using CLK 1
-	register "pch_pcie_rp[PCH_RP(9)]" = "{
-		.clk_src = 1,
-		.clk_req = 1,
-		.flags = PCIE_RP_CLK_REQ_DETECT,
-	}"
-
-	# Enable PCH PCIE RP 11 for optane
-	register "pch_pcie_rp[PCH_RP(11)]" = "{
-		.flags = PCIE_RP_CLK_SRC_UNUSED,
-	}"
-
-	# Hybrid storage mode
-	register "hybrid_storage_mode" = "true"
-
-	# Enable CPU PCIE RP 1 using CLK 0
-	register "cpu_pcie_rp[CPU_RP(1)]" = "{
-		.clk_req = 0,
-		.clk_src = 0,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
-	# Enable CPU PCIE RP 2 using CLK 3
-	register "cpu_pcie_rp[CPU_RP(2)]" = "{
-		.clk_req = 3,
-		.clk_src = 3,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
-	# Enable CPU PCIE RP 3 using CLK 4
-	register "cpu_pcie_rp[CPU_RP(3)]" = "{
-		.clk_req = 4,
-		.clk_src = 4,
-		.flags = PCIE_RP_LTR | PCIE_RP_AER,
-	}"
-
 	register "sata_salp_support" = "1"
 
 	register "sata_ports_enable" = "{
@@ -185,7 +126,6 @@ chip soc/intel/alderlake
 	}"
 
 	device domain 0 on
-		device ref pcie5_0 on end
 		device ref igpu on end
 		device ref dtt on
 			chip drivers/intel/dptf
@@ -297,8 +237,6 @@ chip soc/intel/alderlake
 				device generic 0 on end
 			end
 		end
-		device ref pcie4_0 on end
-		device ref pcie4_1 on end
 		device ref crashlog off end
 		device ref xhci on
 			chip drivers/usb/acpi
@@ -409,11 +347,6 @@ chip soc/intel/alderlake
 				device i2c 36 on end
 			end
 		end
-		device ref pcie_rp5 on end
-		device ref pcie_rp6 on end
-		device ref pcie_rp8 on end
-		device ref pcie_rp9 on end
-		device ref pcie_rp11 on end
 		device ref uart0 on end
 		device ref gspi0 on end
 		device ref p2sb on end
diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
index 8747164f32..be098df1f2 100644
--- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
+++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb
@@ -3,5 +3,58 @@ chip soc/intel/alderlake
 	# seen on J0 and Q0 SKUs
 	register "disable_package_c_state_demotion" = "true"
 
-	device domain 0 on end
+	device domain 0 on
+		register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
+		register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
+		register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING"
+
+		device ref pcie4_0 on
+			register "cpu_pcie_rp[CPU_RP(1)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie4_1 on
+			register "cpu_pcie_rp[CPU_RP(2)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp3 on
+			register "pch_pcie_rp[PCH_RP(3)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp4 on
+			register "pch_pcie_rp[PCH_RP(4)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp5 on
+			register "pch_pcie_rp[PCH_RP(5)]" = "{
+				.clk_src = 1,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp6 on
+			register "pch_pcie_rp[PCH_RP(6)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp7 on
+			register "pch_pcie_rp[PCH_RP(7)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+		device ref pcie_rp8 on
+			register "pch_pcie_rp[PCH_RP(8)]" = "{
+				.clk_src = 0,
+				.flags = PCIE_RP_CLK_REQ_UNUSED,
+			}"
+		end
+	end
 end